16. 3D Chip/Package Co-analysis of Stress-Induced Timing Variations

In this chapter, we study a chip/package stress-aware timing co-analysis methodology for TSV-based 3D ICs. While previous works ignore the stress and mobility variation due to die-stacking and package components, we address these impacts on full-stack 3D IC timing. First, we build hole and electron mobility variation maps based on the chip/package stress co-analysis that considers on/off-chip elements such as TSVs, μ-bumps, and package-bumps ( = C4 bumps). Second, we compare our approach with conventional TSV stress aware timing analysis methods that ignore packaging impacts. Our major finding is that we observe different mobility variation behavior across the stack when we consider both chip and package components. In addition, we observe significant mobility variations in the die closest to the package-bump layer due to the highly compressive stress caused by package-bumps and underfill. Based on these findings, we develop a full-stack 3D static timing analysis engine and provide results for practical 3D IC designs including wide-I/O and block-level 3D ICs.