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Erschienen in:
Patent Issues of Fan-Out Wafer-Level Packaging Kapitel lesen Erstes Kapitel lesen

2018 | OriginalPaper | Buchkapitel

11. 3D IC Heterogeneous Integration by FOWLP

verfasst von : John H. Lau

Erschienen in: Fan-Out Wafer-Level Packaging

Verlag: Springer Singapore

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Abstract

Two 3D IC heterogeneous integrations by Fan-Out Wafer-Level Packaging (FOWLP) technology are presented in this chapter. The emphasis of the first such method is on the design, and of the other method, the emphasis is on the manufacturing process. The heterogeneous integration versus SoC (system-on-chip) will be briefly discussed. Some examples on the TSV (Through-Silicon Via)-less heterogeneous integration by FOWLP will also be presented. Since MCM (Multichip Module) is the frontier of heterogeneous integration and thus it will be briefly mentioned first.

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Vorheriges Kapitel 3D Integration
Literatur
1.
Lau, J.H. 1994. A Brief Interlocution to Wire Bonding, Tape Automated Bonding, and Flip Chip on Board for Multichip Module Applications. In Chip on Board Technologies for Multichip Modules, ed. J.H. Lau, 1–100. New York: Van Nostrand Reinhold.
2.
Lau, J.H. 2013. Through-Silicon Via (TSV) for 3D Integration. New York: McGraw-Hill.
3.
Lau, J.H. 2016. 3D IC Integration and Packaging. New York: McGraw-Hill.
4.
Lau, J.H. 2015. Semiconductor and Packaging for Internet of Things. Chip Scale Review 19: 25–30.
5.
Moore, G. 1965. Cramming More Components Onto Integrated Circuits. Electronics 38 (8).
6.
Jokerst, N.M. 1997. Hybrid Integrated Optoelectronics: Thin Film Devices Bonded to Host Substrates. International Journal of High Speed Electronics and Systems 8 (2): 325–356.CrossRef
7.
Vrazel, M., J. Chang, I. Song, K. Chung, M. Brooke, N. Jokerst, A. Brown, and D. Wills. 2001. Highly Alignment Tolerant InGaAs Inverted MSM Photodetector Heterogeneously Integrated on a Differential Si CMOS Receiver Operating at 1 Gbps. In Proceedings of IEEE/ECTC, May 2001, 1–6.
8.
Jokerst, N.M., M.A. Brooke, S. Cho, S. Wilkinson, M. Vrazel, S. Fike, J. Tabler, Y. Joo, S. Seo, D. Wills, and A. Brown. 2003. The Heterogeneous Integration of Optical Interconnections Into Integrated Microsystems. IEEE Journal of Selected Topics in Quantum Electronics 9 (2): 350–360.CrossRef
9.
Lau, J.H., P. Tzeng, C. Lee, C. Zhan, M. Li, J. Cline, et al. 2014. Redistribution Layers (RDLs) for 2.5D/3D IC Integration. In IMAPS Proceedings, October 2013, 434–441. Also, IMAPS Transactions, Journal of Microelectronic Packaging 11 (1): 16–24.
10.
Li, L., P. Chia, P. Ton, M. Nagar, S. Patil, J. Xie, et al., 3D SiP with Organic Interposer of ASIC and Memory Integration. In IEEE/ECTC Proceedings, 2016, 1445–1450.
11.
Souriau, J., O. Lignier, M. Charrier, and G. Poupon. 2005. Wafer Level Processing of 3D System in Package for RF and Data Applications. In IEEE/ECTC Proceedings, 356–361.
12.
Henry, D., D. Belhachemi, J.-C. Souriau, C. Brunet-Manquat, C. Puget, G. Ponthenier, J. Vallejo, C. Lecouvey, and N. Sillon. 2006. Low Electrical Resistance Silicon Through Vias: Technology and Characterization. In IEEE/ECTC Proceedings, 2006, 1360–1366.
13.
Selvanayagam, C., J.H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T.C. Chai. 2009. Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps. In Proceedings of IEEE/ECTC, May 2008, 1073–1081. Also, IEEE Transactions on Advanced Packaging 32 (4), 720–728 (November 2009).
14.
Chai, T.C., X. Zhang, J.H. Lau, C.S. Selvanayagam, D. Pinjala, Y. Hoe, Y. Ong, V. Rao, E. Wai, H. Li, E. Liao, N. Ranganathan, V. Kripesh, S. Liu, J. Sun, M. Ravi, C. Vath III, and Y. Tsutsumi. 2011. Development of Large Die Fine-Pitch Cu/low-k FCBGA Package with Through Silicon Via (TSV) Interposer. IEEE Transactions on CPMT 1 (5): 660–672.
15.
Banijamali, B., S. Ramalingam, H. Liu, and M. Kim. 2012. Outstanding and Innovative Reliability Study of 3D TSV Interposer and Fine Pitch Solder Micro-bumps. In Proceedings of IEEE/ECTC, May 2012, 309–314.
16.
Chaware, R., K. Nagarajan, and S. Ramalingam. 2012. Assembly and Reliability Challenges in 3D Integration of 28 nm FPGA Die on a Large High Density 65 nm Passive Interposer. In IEEE/ECTC Proceedings, 2012, 279–283.
17.
Banijamali, B., C. Chiu, C. Hsieh, T. Lin, C. Hu, S. Hou, S. Ramalingam, S. Jeng, L. Madden, and D. Yu. 2013. Reliability Evaluation of a CoWoS-Enabled 3D IC Package. In Proceedings of IEEE/ECTC, May 2013, 35–40.
18.
Yu, A., J.H. Lau, S. Ho, A. Kumar, W. Hnin, W. Lee, M. Jong, V. Sekhar, V. Kripesh, D. Pinjala, S. Chen, C. Chan, C. Chao, C. Chiu, C. Huang, and C. Chen. 2011. Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects. IEEE Transactions on CPMT 1 (9): 1336–1344.
19.
Lau, J.H. 2011. Overview and Outlook of TSV and 3D Integrations. Microelectronics International 28 (2): 8–22.CrossRef
20.
Lau, J.H., and G.Y. Tang. 2012. Effects of TSVs (Through-Silicon Vias) on Thermal Performances of 3D IC Integration System-In-Package (SiP). Microelectronics Reliability 52 (11): 2660–2669.CrossRef
21.
Lau, J.H. 2014. The Future of Interposer for Semiconductor IC Packaging. Chip Scale Review 18 (1): 32–36.
22.
Lau, J.H., S. Lee, M. Yuen, J. Wu, J. Lo, H. Fan, and H. Chen. 2013. Apparatus Having Thermal-Enhanced and Cost-Effective 3D IC Integration Structure With Through Silicon Via Interposer. U.S. Patent No. 8,604,603, Filed February 29, 2010 and Issued December 10, 2013.
23.
Bajwa, A., S. Jangam, S. Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, and S.S. Iyer. 2017. Heterogeneous Integration at Fine Pitch (≤10 μm) Using Thermal Compression Bonding. In IEEE/ECTC Proceedings, 2017, 1276–1284.
24.
Lau, J.H. 2016. TSV-Less Interposers. Chip Scale Review 20: 28–35.
25.
Kwon, W., S. Ramalingam, X. Wu, L. Madden, C. Huang, H. Chang, et al. 2014. Cost-Effective and High-Performance 28 nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT). In Proceedings of International Symposium on Microelectronics, 599–605.
26.
Liang, F., H. Chang, W. Tseng, J. Lai, S. Cheng, M. Ma, et al. 2016. Development of Non-TSV Interposer (NTI) for High Electrical Performance Package. In IEEE/ECTC Proceedings, 2016, 31–36.
27.
Hiner, D., M. Kelly, R. Huemoeller, and R. Reed. 2015. Silicon Interposer-Less Integrated Module—SLIM. In International Conference and Exhibition on Device Packaging, 2015.
28.
Chiu, C., Z. Qian, M. Manusharow. 2014. Bridge Interconnect with Air Gap in Package Assembly. US Patent No. 8,872,349.
29.
Mahajan, R., R. Sankman, N. Patel, D. Kim, K. Aygun, Z. Qian, et al. 2016. Embedded Multi-die Interconnect Bridge (EMIB)—A High-Density, High-Bandwidth Packaging Interconnect. In IEEE Proceedings of Electronic Components and Technology Conference, 2016, 557–565.
30.
Pendse, R.D. 2011. Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substruate. Patent Publication No. US2013/0161833A1, Filed on December 23, 2011.
31.
Yoon, S.W., P. Tang, R. Emigh, Y. Lin, P.C. Marimuthu, and R. Pendse. 2013. Fanout Flipchip eWLB (embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions. In Proceedings of IEEE/ECTC, 2013, 1855–1860.
32.
Lin, Y., W. Lai, C. Kao, J. Lou, P. Yang, C. Wang, et al. 2016. Wafer Warpage Experiments and Simulation for Fan-Out Chip-On-Substrate. In IEEE Proceedings of Electronic Components and Technology Conference, 2016, 13–18.
33.
Chen, N., T. Hsieh, J. Jinn, P. Chang, F. Huang, J. Xiao, et al. 2016. A Novel System-In-Package with Fan-Out WLP for High-Speed SERDES Application. In IEEE Proceedings of Electronic Components and Technology Conference, 2016, 1495–1501.
34.
Lau, J.H. 2015. Patent Issues of Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 19: 42–46.
35.
Lau, J.H., N. Fan, M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20: 38–44.
36.
Tseng, C., C. Liu, C. Wu, D. Yu. 2016. InFO (Wafer-Level Integrated Fan-Out) Technology. In IEEE/ECTC Proceedings, June 2016, 1–6.
37.
Hsieh, C., C. Wu, D. Yu. 2016. Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications. In IEEE/ECTC Proceedings, June 2016, 1430–1438.
38.
Lau, J.H., M. Li, D. Tian, N. Fan, E. Kuah, K. Wu, et al. 2017. Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging. In IEEE/ECTC Proceedings, 2017, 595–602. Also, IEEE Transactions on CPMT 7 (10), 1729–1938 (October 2017).
39.
Lau, J.H., M. Li, N. Fan, E. Kuah, Z. Li, K. Tan, T. Chen, et al. 2017. Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs). In IMAPS Proceedings, October 2017, 576–583. Also, IMAPS Transactions, Journal of Microelectronics and Electronic Packaging 14 (4), 123–131 (October 2017).
40.
Li, M., Q. Li, J.H. Lau, N. Fan, E. Kuah, K. Wu, et al. 2017. Characterizations of Fan-Out Wafer-Level Packaging. In IMAPS Proceedings, October 2017, 557–562.
41.
Lau, J.H. 2018. 3D IC Heterogeneous Integration by FOWLP. Chip Scale Review 22: 16–21.
42.
Lau, J.H. 2018. FOWLP for 3D IC Heterogeneous Integration. In IEEE/CSTIC Proceedings, VII. 1–6.
43.
Kuah, E., W. Chan, J. Hao, N. Fan, M. Li, J.H. Lau, et al. 2017. Dispensing Challenges of Large Format Packaging and Some of Its Possible Solutions. In IEEE/EPTC Proceedings, December 2017, S27_1-6.
44.
Hua, X., H. Xu, Z. Li Zhang, D. Chen, K. Tan, J.H. Lau, et al. 2017. Development of Chip-First and Die-Up Fan-Out Wafer-Level Packaging. In IEEE/EPTC Proceedings, December 2017, S23_1-6.
Metadaten
Titel
3D IC Heterogeneous Integration by FOWLP
verfasst von
John H. Lau
Copyright-Jahr
2018
Verlag
Springer Singapore
Buch
Fan-Out Wafer-Level Packaging

Print ISBN: 978-981-10-8883-4

Electronic ISBN: 978-981-10-8884-1

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-981-10-8884-1_11

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