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2017 | Buch

3D Microelectronic Packaging

From Fundamentals to Applications

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SUCHEN

Über dieses Buch

This volume provides a comprehensive reference for graduate students and professionals in both academia and industry on the fundamentals, processing details, and applications of 3D microelectronic packaging, an industry trend for future microelectronic packages. Chapters written by experts cover the most recent research results and industry progress in the following areas: TSV, die processing, micro bumps, direct bonding, thermal compression bonding, advanced materials, heat dissipation, thermal management, thermal mechanical modeling, quality, reliability, fault isolation, and failure analysis of 3D microelectronic packages. Numerous images, tables, and didactic schematics are included throughout. This essential volume equips readers with an in-depth understanding of all aspects of 3D packaging, including packaging architecture, processing, thermal mechanical and moisture related reliability concerns, common failures, developing areas, and future challenges, providing insights into key areas for future research and development.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction to 3D Microelectronic Packaging
Abstract
Advanced 3D microelectronic packaging technology has been employed to meet portable electronics demand of ultra-thin, ultra-light, high performance with low power consumption. It also opens up a new dimension for the semiconductor industry to maintain Moore’s law with a much lower cost. Motivations as well as various architectures of 3D packaging are illustrated. Challenges in 3D packaging, including fabrication, assembly, cost, design, modeling, thermal management, material, substrate, quality, reliability, and failure analysis, are reviewed with brief introduction to the chapters addressing these challenges.
Yan Li, Deepak Goyal
Chapter 2. 3D Packaging Architectures and Assembly Process Design
Abstract
In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking has become a key area of interest for product architects, why it has generated broad industry attention, and why its adoption has been tenous. The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs), while other System In Package (SIP) architectures that do not rely on TSVs are discussed for completeness. The key elements of a TSV-based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e., Via-First, Via-Middle, and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (a) Wafer-to-Wafer (W2W), (b) Die-to-Wafer (D2W), and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process, and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.
Ravi Mahajan, Bob Sankman
Chapter 3. Materials and Processing of TSV
Abstract
This chapter introduces the critical steps involved in fabricating through-silicon vias (TSVs) and associated materials. The fabrication steps for TSVs begin with etching of high aspect ratio trenches in Si, followed by placement of dielectric, barrier and seed layers, TSV filling and polishing, and then assembly with other components of a device. In addition, planarization, die-thinning and flow processes to fabricate TSV-enabled 3-D architectured microelectronic package are described. Challenges associated with processing of TSVs as well as methods for overcoming them are highlighted and discussed.
Praveen Kumar, Indranath Dutta, Zhiheng Huang, Paul Conway
Chapter 4. Microstructural and Reliability Issues of TSV
Abstract
The copper pumping problem exemplifies the complex reliability issues still to be resolved for TSV structures. From a materials science perspective the reliability issues presented by TSVs are linked to manufacturing processes and the resultant microstructure formed. Routine finite element-based reliability studies that treat the TSV filler as an isotropic and homogeneous material are not capable of providing a sufficiently thorough explanation of the observed copper extrusion/intrusion behavior. Rather, the material behavior and properties at multiple scales are required as the input data for effective reliability analysis of three-dimensional TSV stacked ICs. Such 3-D ICs also push the scale of materials to a limit where the anisotropy of material properties, recovery, recrystallization, and time-dependent phase morphological evolution further complicate reliability issues. This chapter reviews both experimental and modeling approaches that address the microstructural and reliability issues of TSVs. Crystal plasticity-based finite element method and phase field crystal method with an inherently multiscale nature are identified as promising modeling techniques to enable atomistically informed reliability analysis of TSVs.
Praveen Kumar, Indranath Dutta, Zhiheng Huang, Paul Conway
Chapter 5. Fundamentals and Failures in Die Preparation for 3D Packaging
Abstract
Through-Silicon-Via (TSV) wafer processes have been reviewed by several authors previously, including temporary adhesive wafer bonding, high aspect ratio silicon etch, and wafer singulation. This chapter starts with a brief overview of TSV wafer fabrication and singulation processes. Then, it focuses on several key process issues which have not been discussed in previous review articles. The first process issue discussed in details here is the device wafer buckling or wrinkling postwafer thinning. This challenge might cause yield loss at the downstream lithography process. The fundamental mechanism behind this issue is investigated and several solutions are proposed. The second process discussed in details here is wafer debonding. Based on viscosity definition and wafer geometry, a closed-form analytical solution is proposed for the thermal sliding wafer debonding process, which can be used for process control and throughput optimization. The next two processes discussed are laser scribe and saw dicing, which impact die edge chipping and low-k inter layer dielectric (ILD) delamination. A closed-form solution of chipping induced by saw dicing is also investigated. The last process discussed in this chapter is the challenges and solution options for die pick and place.
Hualiang Shi, Erasenthiran Poonjolai
Chapter 6. Direct Cu to Cu Bonding and Other Alternative Bonding Techniques in 3D Packaging
Abstract
This chapter provides insights into direct Cu to Cu bonding and summarizes several critical empirical results. After comparing the solder-less Cu–Cu bonding with the solder-based bonding, we introduce various Cu-Cu stacking/bonding schemes for different three-dimensional (3D) integration applications. We then review various methods of low-temperature Cu–Cu bonding including: (a) thermo-compression bonding (diffusion bonding), (b) Cu-Cu bonding with passivation capping layers, (c) surface activated bonding (SAB), and (d) alternative bonding methods (Cu/dielectric hybrid bonding and Cu–Cu insertion bonding). The effects of surface activation, surface microstructures and characteristics, and surface passivation for Cu–Cu bonding are highlighted and discussed to understand how the bonding behavior depends on Cu surface cleanness, diffusion, temperature, compression pressure, and bonding atmosphere. Lastly, we introduce the commercial equipment for Cu–Cu bonding for high-volume manufacturing briefly and summarize with recommendations for future directions. 
Tadatomo Suga, Ran He, George Vakanas, Antonio La Manna
Chapter 7. Fundamentals of Thermal Compression Bonding Technology and Process Materials for 2.5/3D Packages
Abstract
This chapter reviews bonding technology, which would be most problematic among technical challenges, to provide engineering sciences and fundamentals of the bonding technology and process materials. The in situ bonding technology termed as Thermal Compression Bonding (TCB) typically controls force, temperature, and displacement, which are applied to packages when to reflow microbump solder interconnect of 3D TSV die. Consequently, this chapter would help to understand how to design assembly building blocks adequate to the configuration of packages.
Sangil Lee
Chapter 8. Fundamentals of Solder Alloys in 3D Packaging
Abstract
The demand of ever-improving functions of the electronic products has been pushing the development of Moore’s law featuring technologies. The microelectronic circuit technology has been moving towards the single digit nano era which is approaching the current technical limit. 3D packaging technology is being regarded as one of the most feasible technologies in this regard. The chips are being stacked in the 3D packaging so as to efficiently shrink the substrate landscape as well as shorten the circuit distance. The stacking relies on the thumb of art interconnect technologies which allow not only minimizing the substrate area but also the form factor of the products. One of the key interconnect technologies which has been improved to fit the need is the solder bumping. The conventional bumping technology of C4 is being moved to microbump with simplified solder compositions and shrunk solder volume. The dimension of the microbump may be one to three orders less than the C4 bump and BGA solder ball. The fast reaction between solder and the major metallization layers during reflow, thermal compressing bonding, and afterwards functioning results in the vast proportion of intermetallic compounds (IMC) in the smaller solder volume microjoint. The fundamentals to consider about for monitoring the reliability of the microbump will be different from the C4 bump which has large volume fraction of solder alloy. This chapter will discuss the IMC formation and the microstructure of the microbump at the as-produced, thermal cycled stages of the 3D packaging.
Kwang-Lung Lin
Chapter 9. Fundamentals of Electromigration in Interconnects of 3D Packaging
Abstract
Micro bumps, through Si vias (TSV), and redistribution layers (RDL) or back-end-of-line (BEOL) layers that connected to the TSV are unique interconnects connecting the stacked Si dies in 3D packaging. Electromigration (EM) failure has been a concern for these interconnects due to high current density and joule heating. In this chapter, the key EM failure modes in these interconnects are summarized. By leveraging the EM learning from flip chip first-level interconnect solder joints and damascene Cu interconnects, failure mechanisms and factors that modulate the EM of micro bumps, TSV, and its connected Cu layers are also summarized. The impact of the unique micro bump dimensions and structures on EM will be highlighted.
Pilin Liu
Chapter 10. Fundamentals of Heat Dissipation in 3D IC Packaging
Abstract
Cooling of a planar 2D IC chip utilizes heat transfer from a face of the chip through a heat sink. In case of a 3D IC chip stack, the individual chip faces are not available for mounting conventional heat sinks. Mounting the heat sinks on the ends is feasible, but the heat flow paths for the interior chips from the junction to the heat sink become longer. Further, multiple heat sources present along the heat flow paths in stacked chips may create localized hot spots which exceed the allowable junction temperatures. Introducing interlayer cooling with microchannels and introducing fins in the coolant flow paths extend the thermal dissipation capability of a 3D stack; however, this is often accompanied with taller microchannels that lead to longer lengths of through-silicon-vias (TSVs). Placement of TSVs, microchannels walls, and fins present conflicting design requirements. Therefore codesign and innovative approaches are seen as critical before widespread commercialization of 3D ICs becomes a reality. An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this chapter.
Satish G. Kandlikar, Amlan Ganguly
Chapter 11. Fundamentals of Advanced Materials and Processes in Organic Substrate Technology
Abstract
In the past several decades, Moore’s law has successfully predicted integrated circuit (IC) technology advancement. However, IC technology began hitting both technology and cost barriers. Conventional die shrinkage and advanced deep-submicron semiconductor technology is no longer able to meet the cost-to-performance ratio that the world desires in the near future. Three-dimensional (3D) packaging has caught broad attention and is poised to help continue the Moore’s law by vertically integrating multiple IC chips into same footprint. In order to enable highly integrated 3D packaging, both the substrate and the printed wiring board (PWB) receiving the 3D package need to meet the signal and power density requirements. Substrate material and fabrication technologies play critical role in succeeding the future needs of smaller size, lower cost, and higher performance.
In this chapter, an overview of the substrate technology evolution in the past several decades will be discussed. The overview covers the substrates used in large varieties of packages, such as dual-in-line packages (DIP), quad flat package (QFP), area array package, and embedded wafer level ball grid array (eWLB) packages. The materials used in substrates will be discussed with a concentration on organic substrate materials. The discussion will cover key consideration points in material selection and application. The substrate fabrication technology will be also discussed in detail. The process technologies on the fabrication of cores, build-up dielectric layers, metal layers and traces, plated through holes (PTH) and vias, contact pads, solder mask, in addition to surface finishes will be covered. The general recommendation in selecting and applying the appropriate process technologies will be recommended.
Songhua Shi, Peter Tortorici
Chapter 12. Die and Package Level Thermal and Thermal/Moisture Stresses in 3D Packaging: Modeling and Characterization
Abstract
3D packaging employing through-silicon vias (TSVs) to connect multiple stacked dies/chips has great potential to achieve high performance and high capacity with low cost and low energy consumption. However, crucial reliability issues often arise in 3D integrated circuits (ICs) packaging due to high thermal stress and moisture stress at both die and package level. In this chapter, TSV-related reliability issues such as the measurement of thermal stress in TSV, the effect of thermal stress on carrier mobility and keep-out zone, thermal stress induced via extrusion are illustrated. At the package level, various analytical methods for thermal stress-induced warpage in multilayered structures are reviewed. The state-of-the-art approaches for warpage control are presented and validated by experimental testing and numerical modeling. Finally, to incorporate moisture stress that comprehends both hygroscopic stress and the pressure of water vapor, a theoretical framework is provided based on damage micromechanics and the effective stress concept. Some case studies are provided to understand the effect of moisture and vapor pressure.
Liangbiao Chen, Tengfei Jiang, Xuejun Fan
Chapter 13. Processing and Reliability of Solder Interconnections in Stacked Packaging
Abstract
Three-dimensional (3D) packaging, whether stacked die or stacked packages, has been a critical enabler in the further miniaturization and increased functionality of hand-held, consumer electronics. Similarly, reducing the size, weight, and power (SWaP) requirements of high-reliability electronics is an omnipresent goal of the military, space, and satellite communities. Yet, there remains to be an information gap with respect to the long-term performance of 3D packaging in high-reliability electronics that has not been sufficiently addressed by the original equipment manufacturers (OEMs) of consumer products. This chapter helps to fill this gap by highlighting the materials, processes, and growing reliability database of the stacked-package variant within 3D technology. Emphasis is placed on the solder interconnections used to assemble individual packages together as well as the second-level interconnections made between the stacked package and the printed circuit board (PCB). After a brief description of the seemingly divergent reliability requirements between consumer and high-reliability electronics, the discussion turns to the materials and soldering processes used in the assembly of the two common stacked packaging formats—package-on-package (PoP) and package-on-package-on-package (PoPoP). The next section examines solder joint reliability, including service conditions versus accelerated aging tests as well as the impacts of encapsulants and underfills on the long-term performance of PoP and PoPoP interconnections. Particular attention is given to computational modeling that will most certainly be a required toolset for predicting the solder joint reliability of these complex structures. Concluding remarks address the future trends of stacked packages and their potential to significantly enhance the functionality of high-reliability systems while also reducing SWaP.
Paul Vianco
Chapter 14. Interconnect Quality and Reliability of 3D Packaging
Abstract
Quality and reliability aspects of 3D IC and packages are discussed in this chapter. The main focuses are interconnects-related quality and reliability issues. For the 3D packages, interconnects may include microbump, TSV, UBM, copper traces, etc. We compare them to the quality and reliability concerns observed in the existing interconnects, as well as the methodology to predict the field performances. We shall cover microstructure changes and failures driven by mechanical stressing, electromigration (EM), and thermomigration (TM). This way we can see how the transition, for example, from C-4 joints to microbumps may affect the failure modes. On mechanical stressing, we emphasize the brittle nature as well as microvoid formation, especially Kirkendall void formation in microbumps. A string of voids in a brittle material can easily lead to fracture damage. The interest in mechanical failures is because for mobile and wearable devices, the frequency of impact and dropping to the ground is high. On EM and TM in microbumps and TSV, we emphasize the enhanced failure mode due to Joule heating.
Yaodong Wang, Yingxia Liu, Menglu Li, K. N. Tu, Luhua Xu
Chapter 15. Fault Isolation and Failure Analysis of 3D Packaging
Abstract
The high level of functional integration and the complex package architecture in advanced 3D packages pose a significant challenge for conventional Fault Isolation (FI) and Failure analysis (FA) methods. High-resolution nondestructive FI and imaging tools, as well as innovative applications of FA techniques are required to tackle the technical and throughput challenges. In this Chapter, the applications of FI and FA techniques such as Time domain reflectrometry (TDR), Electro Optic Terahertz Pulse Reflectometry (EOTPR), Lock-in Thermography (LIT), Scanning Superconducting Quantum Interference Device (SQUID) Microscopy (SSM), Scanning Acoustic microscopy (SAM), 2D X-ray radiography, 3D X-ray Computed Tomography (CT), laser ablation, Plasma Focused Ion Beam (FIB), Broad-beam Argon Ion Milling, Energy-dispersive X-ray spectroscopy (EDX), X-ray Photoelectron Spectroscopy (XPS), Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS), and Electron Backscatter Diffraction (EBSD) to 3D packages are reviewed along with the key FI and FA challenges. 3D package FA Strategies of building up efficient FI-FA flow and in-depth root cause studies to provide solution paths are discussed and demonstrated by case studies.
Yan Li, Deepak Goyal
Backmatter
Metadaten
Titel
3D Microelectronic Packaging
herausgegeben von
Yan Li
Deepak Goyal
Copyright-Jahr
2017
Electronic ISBN
978-3-319-44586-1
Print ISBN
978-3-319-44584-7
DOI
https://doi.org/10.1007/978-3-319-44586-1

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