3D Microelectronic Packaging

Advanced 3D microelectronic packaging technology has been employed to meet portable electronics and heterogeneous integration roadmap demands of ultra-thin, ultra-light, and high performance with low power consumption. It also opens up a new dimension for the semiconductor industry to maintain Moore’s law with a much lower cost. Motivations as well as various architectures of 3D packaging are illustrated. Challenges in 3D packaging, including fabrication, assembly, cost, design, modeling, thermal management, material, substrate, quality, reliability, and failure analysis, are reviewed with brief introduction to the chapters addressing these challenges.

In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking is a key area of interest for product architects, why it has generated broad industry attention, and why it is seeing increased adoption in recent years (https://​www.​anandtech.​com/​tag/​hbm2 [1; https://​newsroom.​intel.​com/​wp-content/​uploads/​sites/​11/​2019/​08/​Intel-Lakefield-HotChips-presentation.​pdf [2]; Ingerly et al., IEDM [3]; Elsherbini et al., IEDM 4]). The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs). The key elements of a TSV based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e. Via-First, Via-Middle and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (1) Wafer-to-Wafer (W2W) (2) Die-to-Wafer (D2W) and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.

This chapter introduces the critical steps involved in fabricating TSVs and associated materials. The fabrication steps for TSVs begin with etching of high aspect ratio trenches in Si, followed by placement of dielectric, barrier and seed layers, TSV filling and polishing, and then assembly with other components of a device. In addition, planarization, die-thinning and flow processes to fabricate TSV-enabled 3-D architectured microelectronic package are described. Challenges associated with processing of TSVs as well as methods for overcoming them are highlighted and discussed.

The copper pumping problem exemplifies the complex reliability issues still to be resolved for TSV structures. From a materials science perspective the reliability issues presented by TSVs are linked to manufacturing processes and the resultant microstructure formed. Routine finite-element based reliability studies that treat the TSV filler as an isotropic and homogeneous material are not capable of providing a sufficiently thorough explanation of the observed copper extrusion/intrusion behavior. Rather, the material behavior and properties at multiple scales are required as the input data for effective reliability analysis of three- dimensional TSV stacked ICs. Such 3-D ICs also push the scale of materials to a limit where the anisotropy of material properties, recovery, recrystallization and time-dependent phase morphological evolution further complicate reliability issues. This chapter reviews both experimental and modeling approaches that address the microstructural and reliability issues of TSVs. Crystal plasticity based finite element analysis (FEA) and phase field crystal method with an inherently multiscale nature are identified as promising modeling techniques to enable atomistically-informed reliability analysis of TSVs.

With the downscaling of interconnection size, material microstructures are becoming more and more significant in 3D through-silicon via (TSV)-based ICs. To consider material behavior and properties at micro/nanoscale for reliability analysis, robust simulation methods considering microstructures are necessary. This chapter introduces the phase-field-crystal (PFC) model, which resolves materials on atomic length scale and diffusive time scale, and discusses its potential to reveal time-dependent microstructures in TSVs at the nanoscale. PFC models are derived by approximations of system free energy based on the classical density functional theory (CDFT). Approximating the correlation functions using polynomial of different orders can describe various crystal structures, e.g., body-centered cubic (BCC) and face-centered cubic (FCC). Moreover, physical fields occurring in the TSV-based 3D integrations, e.g., strain field, magnetic field and electric field, can also be coupled into the PFC models to simulate the responses of microstructures. Finally, PFC models for TSV-based applications, including filler materials such as copper, tungsten and graphene, are briefly introduced.

Thermal stress-induced protrusion of Cu-TSVs during thermal processing poses substantial reliability concerns in 3D stacked ICs. Following Chap. 5, a two-mode PFC model is used to simulate the microstructural evolution and Cu protrusion of blind TSVs at nanoscale in this chapter. The protrusion behavior under different mechanical loadings is discussed first and then effects of different grain structures on TSV protrusion are presented. The combined effects from both the mechanical loading condition and the Cu grain structures are found to control the complex process of protrusion. Simulation results also suggest that the grains in top end of the TSV contribute more to both the protrusion profile and the protrusion height than the grains below. In addition, the influence of parameters such as temperature and TSV geometry on protrusion are also discussed. General perspectives of TSV protrusion, including atomic mechanisms, criteria to predict the protrusion profile, and a viewpoint from plastic flow are highlighted. The chapter ends up with a discussion on future work to deepen our understanding on TSV protrusion.

Through-Silicon-Via (TSV) wafer processes have been reviewed by several authors previously, including temporary adhesive wafer bonding, high aspect ratio silicon etch, and wafer singulation. This chapter starts with a brief overview of TSV wafer fabrication and singulation processes. Then, it focuses on several key process issues which have not been discussed in previous review articles. First, the temporary wafer bonding process fundamentals, the mechanisms and potential solutions of device wafer buckling or wrinkling, as well as the die-level rippling following wafer bonding and thinning are discussed in detail. Second, the fundamentals and challenges of three main types of wafer debonding processes, along with post debond cleaning, are investigated. Based on the simple viscosity definition and wafer geometry, a closed-form analytical solution is proposed for the thermal slide-off wafer debonding process, which can be used for process control and throughput optimization. The next two processes discussed are laser scribe and saw dicing, which impact die chipping and delamination. A closed-form solution of chipping induced by saw dicing is also investigated. In addition, the challenges and solution options for die eject and attach are discussed. Last but not least, key factors affecting epoxy flow time are studied, and options to reduce the epoxy keep-out-zone (KOZ) are proposed.

This chapter provides insight into direct Cu to Cu bonding and summarizes several critical empirical results. After comparing solder-less Cu–Cu bonding with solder-based bonding, we introduce various Cu–Cu stacking/bonding schemes for different 3D integration applications. We then review a number of methods of low-temperature Cu–Cu bonding including: (a) thermo-compression bonding (diffusion bonding), (b) Cu–Cu bonding with passivation capping layers, (c) surface-activated bonding (SAB) and (d) alternative bonding methods (e.g. Cu/dielectric hybrid bonding and Cu–Cu insertion bonding). The effects of surface activation, surface microstructures and characteristics, and surface passivation on Cu–Cu bonding are highlighted an– discussed to understand how bonding behavior depends on Cu surface cleanness, diffusion, temperature, compression pressure, and bonding atmosphere. Lastly, we briefly introduce the commercial equipment for Cu–Cu bonding for high-volume manufacturing and summarize with recommendations for future research directions.

Copper is a well-known material used for interconnections application. It offers economical advantage over silver and has high electrical conductivity. Studies on copper nano-paste (comprising of monodispersed nano-particles) application on surfaces have reported cracking and a low packing density with high porosity. A novel method utilizing a mixture of copper micron sized particles and nano-particles paste is proposed and investigated. This enables high packing density with low resistivity thus improving the interconnection for low temperature electronics packaging. A model to determine the optimum micro-nano particle size ratio is established to achieve high packing density. The algorithm is based on Monte Carlo method. The modeling results show that a weight ratio of 6.3:1 between micro- and nano- copper particles is predicted to provide maximum packing. Further experiments were carried out to examine the properties of the micro-, nano- and mixed pastes. The paste were prepared in low boiling point organic solvents that are able to evaporate at low temperature. The three kinds of pastes were first inspected under wide-field microscope and scanning electron microscopy (SEM). It is found that the nano-paste has small cracks. In situ temperature and resistance measurements was then used to find transition temperature and electrical conductivity of each kind of paste. After sintering, the mixed paste shows 1.0 Ω of resistance whereas the micro-paste shows 2.3 Ω of resistance. The resistance of nano-paste initially decreases to 1.8 Ω then it shows a rapid increase during sintering due to cracks. Thereafter, packing density of mixed pastes with different ratios was studied and analyzed using SEM and signal processing. The 3:1 mixed paste has lowest porosity and no cracks were observed. The result is also verified by sheet resistance measurement that the 3:1 mixed paste shows only 0.3 Ω/sq as compared to micro-paste which is 3 Ω/sq. The discrepancy in the optimum ratio between simulation and experiments is possibly because the nano-particles are not always arranged around micro-particles as assumed. As a final application, die to wafer bonding has been conducted by using the three types of paste and the bond strength is characterized by shear bond test. Results show that the mixed paste has higher bond strength of 0.7 MPa than micro- and nano- paste of 0.5 and 0.1 MPa, respectively, after bonding at 200 °C without pressure. Therefore, this technique could be used in future applications such as low temperature metal-metal bonding for 3D interconnects application.

A few leading semiconductors recently released high performance products adopting 3-dimensional (3D) packaging technology moved to the forefront in the electronic packaging industry in order to meet the requirements of device performance and form factor driven by consumer electronics trends. Even after 3D commercial products were produced into electronic markets, the leading companies still struggle to demonstrate a competitive 3D packaging assembly process compared to traditional packaging assembly process. In the 3D packaging process, bonding technology among technical challenges is most problematic. The in situ bonding technology referred to as Thermal Compression Bonding (TCB), typically controls force, temperature, and displacement simultaneously, which are applied to packages when to reflow microbump solder interconnect of 3D TSV die. Using the in situ bonding technology, a bonding cycle can be completed in several seconds, which means that bonding equipment and process materials sustain heavy process stress due to rapidly changing thermal conditions. Thus, this chapter reviews the newly developed TCB technology and related assembly materials to provide engineering sciences, fundamentals of the bonding technology, and process materials for advanced application. First, this chapter compares the new technology with traditional assembly process regarding process, material, and equipment. Next, the subsection presents traditional analytical methods and practical fundamental investigation methods to characterize material formulation. Then, a comprehensive analysis is presented to provide the pros and cons of major assembly building blocks. Consequently, this chapter would help to understand how to design assembly building blocks that are adequate to the package configuration. In addition, this chapter introduces a hybrid bonding technology and alternative interconnect technology to overcome throughput challenge induced by TCB bonding mechanism used for 3D stacking.

The demand of ever improving functions of the electronic products has been pushing the development of Moor’s law featuring technologies. The microelectronic circuit technology has been moving towards the single digit nano era which is approaching the current technical limit. 3D packaging technology is being regarded as one of the most feasible technologies in this regard. The chips are being stacked in the 3D packaging so as to efficiently shrink the substrate landscape as well as shorten the circuit distance. The stacking relies on the thumb of art interconnect technologies which allow not only minimizing the substrate area but also the form factor of the products. One of the key interconnect technologies which has been improved to fit the need is the solder bumping. The conventional bumping technology of C4, is being moved to micro-bump with simplified solder compositions and shrunk solder volume. The dimension of the micro-bump may be one to three order less than the C4 bump and BGA solder ball. The fast reaction between solder and the major metallization layers during reflow, thermal compressing bonding, and afterwards functioning results in the vast proportion of intermetallic compounds (IMC) in the smaller solder volume micro joint. The fundamentals to consider about for monitoring the reliability of the microbump will be different from the C4 bump which has large volume fraction of solder alloy. This chapter will discuss the IMC formation and the microstructure of the microbump at the as-produced, thermal cycled stages of the 3D packaging.

Micro bumps, through Si vias (TSV), and redistribution layers (RDL) or back-end-of-line (BEOL) layers that connected to the TSV are unique interconnects connecting the stacked Si dies in 3D packaging. Electromigration (EM) failure has been a concern for these interconnects due to high current density and joule heating. In this chapter, the key EM failure modes in these interconnects are summarized. By leveraging the EM learning from flip chip first level interconnect solder joints and damascene Cu interconnects, failure mechanisms and factors that modulate the EM of micro bumps, TSV and its connected Cu layers are also summarized. The impact of the unique micro bump dimensions and structures on EM will be highlighted.

Cooling of a planar 2D IC chip utilizes heat transfer from a face of the chip though a heat sink. In case of a 3D IC chip stack, the individual chip faces are not available for mounting conventional heat sinks. Mounting the heat sinks on the ends is feasible, but the heat flow paths for the interior chips from the junction to the heat sink become longer. Further, multiple heat sources present along the heat flow paths in stacked chips may create localized hot spots which exceed the allowable junction temperatures. While 2.5D integration in complex ICs where individual layers are mounted on another base die called an interposer can alleviate the heat dissipation issues, it cannot deliver the benefits of monolithic 3D ICs due to the planar distance between the chips or chiplets over the interposer. Introducing interlayer cooling with microchannels and introducing fins in the coolant flow paths extend the thermal dissipation capability of a 3D stack; however this is often accompanied with taller microchannels that lead to longer lengths of through-silicon-vias (TSVs). Placement of TSVs, microchannels walls and fins present conflicting design requirements. Therefore co-design and innovative approaches are seen as critical before widespread commercialization of 3D ICs becomes a reality. An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this chapter.

In the past several decades, Moore’s law has successfully predicted integrated circuit (IC) technology advancement. However, IC technology began hitting both technology and cost barriers. Conventional die shrinkage and advanced deep-submicron semiconductor technology is no longer able to meet the cost-to-performance ratio that the world desires in the near future. Three dimensional (3D) packaging has caught broad attention and is poised to help continue the Moore’s law by vertically integrating multiple IC chips into same footprint. In order to enable highly integrated 3D packaging, both the substrate and the printed circuit board (PCB) receiving the 3D package need to meet the signal and power density requirements. Substrate material and fabrication technologies play critical role in succeeding the future needs of smaller size, lower cost, and higher performance. In this chapter, an overview of the substrate technology evolution in the past several decades will be discussed. The overview covers the substrates used in large varieties of packages, such as dual-in-line packages (DIP), quad flat package (QFP), area array package, and embedded wafer level ball grid array (eWLB) packages. The materials used in substrates will be discussed with a concentration on organic substrate materials. The discussion will cover key consideration points in material selection and application. The substrate fabrication technology will be also discussed in detail. The process technologies on the fabrication of cores, build-up dielectric layers, metal layers and traces, plated through holes (PTH) and vias, contact pads, solder mask, in addition to surface finishes will be covered. The general recommendation in selecting and applying the appropriate process technologies will be recommended.

3D packaging employing through-silicon vias (TSVs) to connect multiple stacked dies/chips has great potential to achieve high performance and high capacity with low cost and low energy consumption. However, crucial reliability issues often arise in 3D integrated circuits (ICs) packaging due to high thermal stress and moisture stress at both die and package level. In this chapter, TSV related reliability issues such as the measurement of thermal stress in TSV, the effect of thermal stress on carrier mobility and keep-out zone, thermal stress induced via extrusion are illustrated. At the package level, various analytical methods for thermal-stress induced warpage in multi-layered structures are reviewed. The state-of-the-art approaches for warpage control are presented and validated by experimental testing and numerical modeling. Finally, to incorporate moisture stress that comprehends both hygroscopic stress and the pressure of water vapor, a theoretical framework is provided based on damage micromechanics and the effective stress concept. Some case studies are provided to understand the effect of moisture and vapor pressure.

Three-dimensional (3-D) packaging, whether stacked die or stacked packages, has been a critical enabler in the further miniaturization and increased functionality of hand-held, consumer electronics. Similarly, reducing the size, weight, and power (SWaP) requirements of high-reliability electronics is an omnipresent goal of the military, space, and satellite communities. Yet, there remains an information gap with respect to the long-term performance of 3-D packaging in high-reliability electronics. This chapter helps to fill this gap by highlighting the materials, processes, and growing reliability database of the stacked-package variant within 3-D technology. Emphasis is placed on the first-level solder interconnections used to assemble individual packages together as well as the second-level solder joints made between the stacked package and the printed circuit board (PCB). After a brief description of the seemingly divergent reliability requirements between consumer and high-reliability electronics, the discussion turns to the materials and soldering processes used in the assembly of the two common stacked packaging formats—package-on-package (PoP) and package-on-package-on-package (PoPoP). The next section examines solder joint reliability, including service conditions versus accelerated aging tests as well as the impacts of conformal coatings and underfills on the long-term performance of PoP and PoPoP interconnections. Particular attention is given to the critical role that computational modeling has for predicting solder joint reliability resulting from the complexity of PoP and PoPoP structures. Concluding remarks address the future trends of stacked packages and their potential to significantly enhance the functionality of high-reliability systems.

Quality and reliability aspects of 3D IC and packages are discussed in this chapter. The main focuses are interconnects related quality and reliability issues. For the 3D packages, interconnects may include microbump, TSV, UBM and copper traces etc. We compare them to the quality and reliability concerns observed in the existing interconnects, as well as eh methodology to predict the field performances. We shall cover microstructure changes and failures driven by mechanical stressing, electromigration (EM), and thermomigration (TM). This way we can see how the transition, for example, from C-4 joints to microbumps, may affect the failure modes. On mechanical stressing, we emphasize the brittle nature as well as micro-void formation, especially Kirkendall void formation in microbumps. A string of voids in a brittle material can easily lead to fracture damage. The interest in mechanical failures is because for mobile and wearable devices, the frequency of impact and dropping to the ground is high. On EM and TM in microbumps and TSV, we emphasize the enhanced failure mode due to Joule heating.

The high level of functional integration and the complex package architecture in advanced 3D packages pose a significant challenge for conventional Fault Isolation (FI) and Failure analysis (FA) methods. High resolution non-destructive FI and imaging tools, as well as innovative applications of FA techniques are required to tackle the technical and throughput challenges. In this chapter, the applications of FI and FA techniques such as Time domain reflectometry (TDR), Electro Optic Terahertz Pulse Reflectometry (EOTPR), Lock-in Thermography (LIT), Scanning Superconducting Quantum Interference Device (SQUID) Microscopy (SSM), Scanning Acoustic microscopy (SAM), Infrared (IR) imaging, 2D X-ray radiography, 3D X-ray Computed Tomography (CT), laser ablation, Plasma Focused Ion Beam (FIB), Broad-beam Ion Milling, Energy-dispersive X-ray spectroscopy (EDX), X-ray Photoelectron Spectroscopy (XPS), Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS), Fourier transform infrared (FTIR), AFM-based infrared spectroscopy (AFM-IR), and Electron Backscatter Diffraction (EBSD) to 3D packages are reviewed along with the key FI and FA challenges. 3D package FA Strategies of building up efficient FI-FA flow, and in-depth root cause studies to provide solution paths are discussed and demonstrated by case studies.