Three-dimensional (3D) stress, process and device simulation is performed for nMOS-FETs with widths from 0.5 µm to 0.1 µm and gate lengths from 100 nm to 45 nm. Stress originates from a cap-liner with 2 GPa tensile stress. Drift-diffusion simulation with the linear piezoresistance model is employed considering either the position-dependence of stress or using a constant stress tensor obtained from averaging the stress in the source-side of the channel over a cuboid extending over the full device width.
Considering a space-dependent or a constant stress tensor turns out to yield almost the same linear and saturation current enhancements. This permits to use the constant stress obtained from 3D stress simulation for much faster 2D process and device simulation. In particular, also only one band structure is needed for Monte Carlo device simulation.