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Über dieses Buch

This book discusses design techniques, layout details and measurements of several key analog building blocks that currently limit the performance of 5G and E-Band transceivers implemented in deep-scaled CMOS. The authors present recent developments in low-noise quadrature VCOs and tunable inductor-less frequency dividers. Moreover, the design of low-loss broadband transformer-based filters that realize inter-stage matching, power division/combining and impedance transformation is discussed in great detail. The design and measurements of a low-noise amplifier, a downconverter and a highly-linear power amplifier that leverage the proposed techniques are shown. All the prototypes were realized in advanced nanometer scaled CMOS technologies without RF thick to metal option.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
The evolution of mobile communication has a deep impact on the daily life of millions of people all over the world. In just a few decades, we have witnessed a revolution in the way people communicate, share ideas and live. This is still happening and will continue in the future. The 1G analog cellular system was introduced in the ’80s. But it is only with the 2nd generation 2G and the switch to digital cellular system that in the ’90s the mobile communication reached the mass level production, connecting people all over the world. Today, thanks to 3G (’00s) and 4G (’10s) people are able to use mobile devices to connect to the internet. This phenomenon is referred as people-to-thing communication.
Marco Vigilante, Patrick Reynaert

Chapter 2. G Stage and Passives in Deep-Scaled CMOS

Abstract
CMOS technology scaling allows faster transistors at each node, making mm-Wave analog design possible. However, scaling does not provide only benefits. The lower break down voltage forces the scaling of the voltage power supply as well, posing severe limitations on linearity, device stacking and achievable signal-to-noise ratio. The back end of line (BEOL) metal stack gets thinner and closer to the substrate, making the effect of interconnection losses and parasitics dominant. Moreover, mm-Wave design is to some extend an upside down world when compared to RF design (in the low GHz range). At RF frequencies, capacitors show higher quality factor when compared to inductors. On-chip transmission lines are almost impossible to realize due to the large wavelength. At mm-Wave however the scenario is completely the opposite. Therefore, new design techniques are needed to face such technology constrains. This chapter deals with the basic blocks available to analog designers in deep-scaled CMOS. The active devices are the focus of Sect. 2.1. Passive devices are discussed in Sect. 2.2. The aim is to briefly recall the basic of operation with a strong focus on the major challenges that a designer faces at mm-Wave. The effect of scaling is also discussed, leading to simple design guidelines and establishing the foundation of the following chapters.
Marco Vigilante, Patrick Reynaert

Chapter 3. Gain-Bandwidth Enhancement Techniques for mm-Wave Fully-Integrated Amplifiers

Abstract
This chapter recalls filter basics and introduces design techniques to achieve gain-bandwidth enhancement and further approach the Bode-Fano limit. A strong focus is put on filter topologies that lead to relatively easy implementation with on-chip components and have shown state-of-the-art performance at mm-Wave.
Marco Vigilante, Patrick Reynaert

Chapter 4. mm-Wave LC VCOs

Abstract
The phase noise (PN) at the output of the phase locked loop (PLL) sets a fundamental limit to the maximum spectral efficiency that the whole system can achieve. As discussed in Chap. 1, the bit error rate against SNR requirements in an AWGN environment shown in Fig. 1.​7 changes drastically when a practical PN profile is considered, see Fig. 1.​16. Moreover, together with the tough PN requirements, a PLL should be able to synthesize the necessary LO signal over the whole band of operation.
Marco Vigilante, Patrick Reynaert

Chapter 5. mm-Wave Dividers

Abstract
The PLL is a key subsystems of any transceiver for wireless applications. In state-of-the-art fundamental mm-Wave PLL (both analog and digital) the first divider and oscillator run at the highest frequency, becoming the system bottleneck for noise, tuning-range, power consumption and yield under PVT variation (X. Yi et al. in IEEE J Solid-State Circuits 49(2);347–359 (2014) [1], (W. Wu et al. in IEEE J. Solid-State Circuits 49(5);1081–1096, 2014) [2]. It is therefore highly desirable to adopt robust low power solutions for the frequency divider, with possibly a large tuning capability to overcome the variation. Injection locked (IL) LC frequency dividers achieve the higher speed for a given power consumption but need one or even more on-chip inductors rising the complexity of the design and yielding a large area consumption for a limited locking range (LR) (Yamamoto and Fujishima in IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2006) [3], (Chen et al. in IEEE Trans. Microw. Theory Tech. 57(12);3060–3069, 2009) [4], (Yu et al. in IEEE Microw. Wirel. Compon. Lett. 22(2), 82–84, 2012) [5], (Wu in IEEE Trans. Circuits Syst. I Regul. Pap. 60(8);2001–2008, 2013) [6], (Katayama et al. in IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Sendai, 2015) [7]. Static CML dividers, on the other hand, are famous for the wide LR, but require a large power consumption to work at high speed, even if inductive peaking techniques are used (Li et al. in Proceedings of ESSCIRC, Seville, 2010) [8]. In (Ghilioni et al. in IEEE J. Solid-State Circuits 48(8);1842–1850, 2013) [9] an RC static divider based on CML dynamic latches with load modulation is proposed. This topology, derived by the traditional CML static one, improves the divider performance at high frequencies, leading to a low power tunable solution. This chapter is organized as follow. The basic concept of injection locking is revised in Sect. 5.1. This technique is particularly powerful and commonly adopted by many state-of-the-art high speed low power frequency dividers and multipliers. It is also useful to study the effect of coupled oscillators (such as quadrature VCOs) and the undesired effect of pulling between two VCOs running at different frequencies on the same chip and/or between the VCO and the power amplifier in a direct conversion transmitter (Razavi in IEEE J. Solid-State Circuits 39(9);1415–1424, 2004) [10], (Mirzaei et al. in IEEE J. Solid-State Circuits 42(9);1916–1932, 2007) [11], (Mirzaei et al. in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014) [12]. Section 5.2 recalls the most popular circuits used in state-of-the-art high speed dividers. The operation principle of each solution is briefly summarized and the design trade-offs are highlighted. Section 5.3 presents a systematic design methodology to maximize performance of RC static divider based on CML dynamic latches with load modulation in the frequency band from 60 to 90 GHz. A divide-by-4 prototype 28 nm bulk CMOS based on the proposed design techniques is fully characterized, demonstrating a measured operating range from 25 to 102 GHz, when drawing 2.81–5.64 mW from a 0.9 V supply.
Marco Vigilante, Patrick Reynaert

Chapter 6. mm-Wave Broadband Downconverters

Abstract
This chapter is devoted to receiver (RX) front-ends for mm-Wave applications. As discussed in Chap. 1 the RX sensitivity sets a straightforward limit to the achievable link distance. Moreover, to achieve wideband operation without jeopardizing the insertion loss of the required matching networks, the design techniques discussed in Chap. 3 are largely employed. The design challenges and trade-offs relevant to mm-Wave circuits implemented in deep-scaled CMOS are addressed.
Marco Vigilante, Patrick Reynaert

Chapter 7. mm-Wave Highly-Linear Broadband Power Amplifiers

Abstract
In Chap. 1 the system level requirements in terms of TX bandwidth and linearity were addressed. Chapter 2 introduced the design challenges of deep-scaled CMOS actives and passives components and in Chap. 3 several gain-bandwidth enhancement techniques were considered. This chapter brings these results together and applies them to mm-Wave broadband CMOS power amplifiers (PAs) design.
Marco Vigilante, Patrick Reynaert

Chapter 8. Conclusion

Abstract
A new era is fast approaching. Up to hundred devices and sensors will surround every person, spanning from simple low cost disposable sensors, to smart watches and wearables, from car radar for adaptive cruise control, blind spot detection, etc. to self driving car, not to mention high quality video applications for smartphones, tablet and 360\({^{\circ }}\) virtual reality. To enable this revolution 100\(\times \) higher data rate, 100\(\times \) higher network efficiency and better than 1 ms latency are needed. To ensure low cost and mass production capabilities CMOS technology will play a key role. Therefore, design techniques for broadband and low power building blocks for mm-Wave transceivers integrated in deep-scaled CMOS are attracting an ever increasing attention from industries and research institutes.
Marco Vigilante, Patrick Reynaert

Backmatter

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