Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

5. A 2 GHz Continuous-Time ΔΣ ADC with Dynamic Error Correction

verfasst von : Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Erschienen in: High Speed and Wide Bandwidth Delta-Sigma ADCs

Verlag: Springer International Publishing

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

In the previous chapter, we have presented the design and implementation details of a 3rd order 4-bit continuous-time delta-sigma (CTΔΣ) ADC which uses a high-speed filter topology. However, its signal-to-noise ratio (SNR) and signal-to-noise-and-distortion ratio (SNDR) are limited to 65.5 and 65 dB at −0.5 dBFS input, respectively. The main reason for this is that for large input signals, the non-linearity of the 4-bit feedback DAC (DAC1) causes harmonic components and quantization noise to fold into the signal band, which increases the in-band noise. In order to improve the SNR and SNDR of the modulator, the non-linearity of the multi-bit DAC1 must be tackled. This chapter discusses how to do this, and in particular, how to improve the high frequency linearity of DAC1 without degrading the stability of the modulator.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel A 4 GHz Continuous-Time ΔΣ ADC
Nächstes Kapitel Conclusions
Fußnoten
1
In this work, we prefer to call it an error-switching (ES) technique because it more suitably describes the working principle of the scheme.
 
2
The timing of DAC2 and quantizer, which have not been modified, are shown in Figs. 3.​27b and 4.​4, respectively.
 
Literatur
1.
K. Doris, A.H.V. Roermund, D. Leenaerts, Wide-Bandwidth High Dynamic Range D/A Converters (Springer, Dordrecht, 2006)
2.
T. Yongjian, H. Hegt, A. van Roermund, Dynamic-Mismatch Mapping for Digitally-Assisted DACs (Springer, New York, 2013)
3.
C.-H. Lin et al., A 12 bit 2.9 GS/s DAC with IM3 < −60 dBc beyond 1 GHz in 65 nm CMOS. IEEE J. Solid-State Circuits 44(12), 3285–3293 (2009)
4.
B. Schafferer, R. Adams, A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2004), San Francisco, Feb 2004, vol. 1, pp. 360–532
5.
A. van den Bosch, M. Borremans, M. Steyaert, W. Sansen, A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J. Solid-State Circuits 36(3), 315–324 (2001)CrossRef
6.
P. Drennan, C. McAndrew, Understanding MOSFET mismatch for analog design. IEEE J. Solid-State Circuits 38(3), 450–456 (2003)CrossRef
7.
P. Palmers, M. Steyaert, A 11 mW 68dB SFDR 100 MHz bandwidth ΣΔ-DAC based on a 5-bit 1GS/s core in 130nm, in 34th European Solid-State Circuits Conference (ESSCIRC 2008), Edinburgh, Sept 2008, pp. 214–217
8.
W. Schofield, D. Mercer, L. Onge, A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral density, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2003), San Francisco, 2003, vol. 1, pp. 126–482
9.
R. Baird, T. Fiez, Improved ΔΣ DAC linearity using data weighted averaging, in IEEE International Symposium on Circuits and Systems (ISCAS’95), Seattle, Apr 1995, vol. 1, pp. 13–16
10.
C. Conroy, W. Lane, M. Moran, Statistical design techniques for D/A converters. IEEE J. Solid-State Circuits 24(4), 1118–1128 (1989)CrossRef
11.
T. Chen, G. Gielen, A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration. IEEE J. Solid-State Circuits 42(11), 2386–2394 (2007)CrossRef
12.
Z. Li, T. Fiez, A 14 bit continuous-time delta-sigma A/D modulator with 2.5 MHz signal bandwidth. IEEE J. Solid-State Circuits 42(9), 1873–1883 (2007)
13.
P. Witte, J. Kauffman, J. Becker, Y. Manoli, M. Ortmanns, A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2012), San Francisco, Feb 2012, pp. 154–156
14.
K. Doris, J. Briaire, D. Leenaerts, M. Vertreg, A. van Roermund, A 12b 500MS/s DAC with > 70dB SFDR up to 120MHz in 0.18μm CMOS, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2005), San Francisco, Feb 2005, vol. 1, pp. 116–588
15.
L. Risbo et al., Digital approaches to ISI-mitigation in high-resolution oversampled multi-level D/A converters. IEEE J. Solid-State Circuits 46(12), 2892–2903 (2011)CrossRef
16.
M. Bolatkale, L. Breems, R. Rutten, K. Makinwa, A 4 GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2011), San Francisco, Feb 2011, pp. 470–472
17.
H. Shibata et al., A DC-to-1GHz tunable RF ΔΣ ADC achieving DR=74dB and BW=150MHz at f 0=450MHz using 550mW, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 2012), San Francisco, Feb 2012, pp. 150–151
18.
R.W. Adams, Design and implementation of an audio 18-bit analog-to-digital converter using oversampling techniques. J. Audio Eng. Soc. 34(3), 153–166 (1986)
19.
E. van der Zwan, E. Dijkmans, A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range. IEEE J. Solid-State Circuits 31(12), 1873–1880 (1996)
20.
S. Park, G. Kim, S.-C. Park, W. Kim, A digital-to-analog converter based on differential-quad switching. IEEE J. Solid-State Circuits 37(10), 1335–1338 (2002)CrossRef
21.
K. Nguyen, R. Adams, K. Sweetland, H. Chen, A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio. IEEE J. Solid-State Circuits 40(12), 2408–2415 (2005)CrossRef
Metadaten
Titel
A 2 GHz Continuous-Time ΔΣ ADC with Dynamic Error Correction
verfasst von
Muhammed Bolatkale
Lucien J. Breems
Kofi A. A. Makinwa
Copyright-Jahr
2014
Buch
High Speed and Wide Bandwidth Delta-Sigma ADCs

Print ISBN: 978-3-319-05839-9

Electronic ISBN: 978-3-319-05840-5

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-319-05840-5_5

Neuer Inhalt

    Bildnachweise