nach oben

Journal of Computational Electronics

Erschienen in:

05.09.2018

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

verfasst von: Suman Kr. Mitra, Brinda Bhowmick

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2018

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config

KI-gestützte Suche

Aus

Abstract

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.

Vorheriger Artikel A quantum kinetic approach for calculating low-field mobility in black phosphorus crystals and multilayer phosphorene

Nächster Artikel Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 340 Zeitschriften

aus folgenden Fachgebieten:

Bauwesen + Immobilien
Business IT + Informatik
Finance + Banking
Management + Führung
Marketing + Vertrieb
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Nur mit Berechtigung zugänglich

Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.S.P.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3), 259–288 (2001). https://doi.org/10.1109/5.915374 CrossRef

Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy efficient electronic switches. Nature 479(7373), 329–337 (2011). https://doi.org/10.1038/nature10679 CrossRef

Le Royer, C., Mayer, F.: Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture. In: Proc. 10th Int. Conf. Ultimate Integr. Silicon, (ULIS), pp. 53–56, Aachen (2009). https://doi.org/10.1109/ulis.2009.4897537

Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Dev. Lett. 28(8), 743–745 (2007). https://doi.org/10.1109/LED.2007.901273 CrossRef

Avci, U.E., Morris, D.H., Young, I.A.: Tunnel field-effect transistors: prospects and challenges. IEEE J. Electron Dev. Soc. 3(3), 88–95 (2015). https://doi.org/10.1109/JEDS.2015.2390591 CrossRef

International Technology Roadmap for Semiconductors (Online). http://www.itrs.net/

Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Dev. 54(7), 1725–1733 (2007). https://doi.org/10.1109/TED.2007.899389 CrossRef

Goswami, R., Bhowmick, B., Baishya, S.: Physics-based surface potential electric field and drain current model of a δp ⁺ Si_1–xGe_x gate–drain underlap nanoscale n-TFET. Int. J. Electron. 103(9), 1566–1579 (2016). https://doi.org/10.1080/00207217.2016.1138514 CrossRef

Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤ 50 mV/decade) at room temperature. IEEE Electron Dev. Lett. 32(4), 437–439 (2011). https://doi.org/10.1109/LED.2011.2106757 CrossRef

10.

Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with < 50-mV/decade subthreshold swing. IEEE Electron Dev. Lett. 32(11), 1504–1506 (2011). https://doi.org/10.1109/LED.2011.2165331 CrossRef

11.

Vishnoi, R., Kumar, M.J.: Compact analytical drain current model of gate-all-around nanowire tunneling FET. IEEE Trans. Electron Dev. 61(7), 2599–2603 (2014). https://doi.org/10.1109/TED.2014.2322762 CrossRef

12.

Mehta, J.U., Borders, W.A., Liu, H., Pandey, R., Datta, S., Lunardi, L.: III–V tunnel FET model with closed-form analytical solution. IEEE Trans. Electron Dev. 63(5), 2163–2168 (2016). https://doi.org/10.1109/TED.2015.2471808 CrossRef

13.

Beneventi, G.B., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Dual-metal-gate InAs tunnel FET with enhanced turn-on steepness and high on-current. IEEE Trans. Electron Dev. 61(3), 776–784 (2014). https://doi.org/10.1109/TED.2014.2298212 CrossRef

14.

Kao, K., Member, S., Verhulst, A.S., Vandenberghe, W.G., Sorée, B., Magnus, W., Leonelli, D., Member, S., Groeseneken, G., Meyer, K.De: Optimization of gate-on-source-only tunnel FETs with counter-doped pockets. IEEE Trans. Electron Dev. 59, 2070–2077 (2012). https://doi.org/10.1109/TED.2012.2200489 CrossRef

15.

Yang, Z.: Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Dev. Lett. 37(7), 839–842 (2016). https://doi.org/10.1109/LED.2016.2574821 CrossRef

16.

Ohno, T., Kado, Y., Harada, M., Tsuchiya, T.: Experimental 0.25-μm-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique. IEEE Trans. Electron Dev. 42(8), 1481–1486 (1995). https://doi.org/10.1109/16.398663 CrossRef

17.

Goswami, R., Bhowmick, B.: An analytical model of drain current in a nanoscale circular gate TFET. IEEE Trans. Electron Dev. 64(1), 45–51 (2017). https://doi.org/10.1109/TED.2016.2631532 CrossRef

18.

TCAD Sentaurus Device User’s Manual, Synopsys, Inc., Mountain View, CA, USA (2010)

19.

Mitra, S.K., Goswami, R., Bhowmick, B.: A hetero-dielectric stackgate SOI-TFET with back gate and its application as a digital inverter. Superlattice Microstruct. 92, 37–51 (2016). https://doi.org/10.1016/j.spmi.2016.01.040 CrossRef

20.

Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.: Pseudo two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Dev. 57(4), 827–834 (2010). https://doi.org/10.1109/TED.2010.2040661 CrossRef

21.

Vandenberghe, W., Verhulst, A.S., Groeseneken, G., Soree, B., Magnus, W.: Analytical model for point and line tunneling in a tunnel field-effect transistor. In: Proc. Int. Conf. SISPAD, pp. 137–140 (2008). https://doi.org/10.1109/sispad.2008.4648256

22.

Aydin, C., Zaslevsky, A., Luryi, S., Cristoloveanu, S., Mariolle, D., Fraboulet, D., Deleonibus, S.: Lateral interband tunneling transistor in silicon-on-insulator. Appl. Phys. Lett. 84(10), 1780–1782 (2004). https://doi.org/10.1063/1.1668321 CrossRef

23.

Lee, G., Jang, J.-S., Choi, W.Y.: Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors. Semicond. Sci. Technol. 28, 052001 (2013). https://doi.org/10.1088/0268-1242/28/5/052001 CrossRef

24.

Kumar, M.J., Chaudhry, A.: Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans. Electron Dev. 51(4), 569–574 (2004). https://doi.org/10.1109/TED.2004.823803 CrossRef

25.

Hraziia, A., Vladimirescu, A., Amara, A., Anghel, C.: An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid-State Electron. 70, 67–72 (2012). https://doi.org/10.1016/j.sse.2011.11.009 CrossRef

26.

Sze, S.M., Kwok, K.N.: Physics of Semiconductor Devices. Wiley, New York (2007)

27.

De Michielis, L., Lattanzio, L., Moselund, K.E., Riel, H., Ionescu, A.M.: Tunneling and occupancy probabilities: how do they affect tunnel-FET behavior? IEEE Electron Dev. Lett. 34, 726–728 (2013). https://doi.org/10.1109/LED.2013.2257665 CrossRef

28.

Majkusiak, B., Badri, M.H.: Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide. IEEE Trans. Electron Dev. 47, 2347–2351 (2000). https://doi.org/10.1109/16.887019 CrossRef

29.

Neamen, D.A.: Semiconductor Physics and Devices: Basic Principles. McGraw-Hill, New York (2012)

30.

Bhushan, B., Nayak, K., Rao, V.R.: DC compact model for SOI tunnel field-effect transistors. IEEE Trans. Electron Dev. 59(10), 2635–2642 (2012). https://doi.org/10.1109/TED.2012.2209180 CrossRef

31.

Schenk, A.: Rigorous theory and simplified model of the band-to-band tunneling in silicon. Solid-State Electron. 36(1), 19–34 (1993). https://doi.org/10.1016/0038-1101(93)90065-X CrossRef

32.

Biswas, A., Dan, S.S., Royer, C.L., Grabinski, W., Ionescu, A.M.: TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Microelectron. Eng. 98, 334–337 (2012). https://doi.org/10.1016/j.mee.2012.07.077 CrossRef

Titel: A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs
verfasst von: Suman Kr. Mitra
Brinda Bhowmick
Publikationsdatum: 05.09.2018
Verlag: Springer US
Erschienen in: Journal of Computational Electronics / Ausgabe 4/2018
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-018-1236-3

Neuer Inhalt

Bildnachweise

VDI-Icon, Profil Icon, inhalt2, Springer Professional Modul/© Springer Fachmedien Wiesbaden GmbH, Nachhaltigkeitsaward Key Visual/© Cometis AG/Global ESG Monitor | Daniel Rupp | Generiert mit KI, Search Icon, Banner Hanser, Beijing Auto Show 2024: Deutsche Hersteller wollen angreifen./© EKH-Pictures / Generated with AI / Stock.adobe.com, Buchstaben, die aus einem Megaphon kommen/© MicroStockHub/Getty Images/iStock, Digitale Lieferkette/© zapp2photo / stock.adobe.com, Zeitschrift Wissensmanagement Cover, PatentFit-Logo/© Springer Fachmedien Wiesbaden GmbH, Sustainibility Finance/© Robert Kneschke / stock.adobe.com / Springer Fachmedien Wiesbaden GmbH, Zukunftswerkstatt Sales Excellence 2024/© AndreyPopov / Getty Images / iStock, 2023_Antrieb/© supervisuell

Springer Professional

Abstract

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Springer Professional "Wirtschaft"

Weitere Artikel der Ausgabe 4/2018

Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method

EMA-based modeling of the surface potential and drain current of dual-material gate-all-around TFETs

3D numerical simulations of single-event transient effects in SOI FinFETs

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

Atomistic tight-binding theory for acceptor states (C, Be, Mg, Zn, Si and Cd) of GaAs nanocrystals

First-principles study of efficient phenothiazine-based D–π–A organic sensitizers with various spacers for DSSCs

Neuer Inhalt

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.