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Aggressive technology shrinking has increased the sensitivity of integrated circuits in terms of devices ageing. As a result, the performance of a CMOS device will degrade significantly over time and, therefore, results in the delay faults. In situ delay fault monitoring schemes have been proposed to ensure the reliability of an IC during its lifetime. Such schemes are usually based on the application of ageing sensors to predict ageing-induced failures of a circuit and react accordingly. Traditional ageing sensors are implemented on the near-critical paths, which are considered as the most vulnerable paths to delay faults caused by performance degradation. However, today’s complex designs and technology node shrinking have enhanced the number of near- and potential critical paths that need to be monitored. This means the in situ delay fault monitoring approaches are becoming very expensive and may be infeasible. This chapter introduces a state-of-the-art in situ delay monitor called Differential Multiple Error Detection Sensor (DMEDS). The chapter presents a case study to demonstrate how the DMEDS monitors multiple paths simultaneously, and it discusses the advantages and disadvantages of this proposed approach compared with the traditional techniques.
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- A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring
- Chapter 8