A Customized Hardware Architecture for Multi-layer Artificial Neural Networks on FPGA

This paper presents a novel and customized hardware architecture for the realization of artificial neural networks on reconfigurable computing platforms like FPGAs. The proposed architecture employs only one single-hardware-computing layer (namely SHL-ANN) to perform the whole computing fabric of multi-layer feed-forward neural networks. The 16-bit half-precision floating-point number format is used to represent the weights of the designed network. We investigate the scalability and hardware resource utilization of the proposed neural network architecture on the Xilinx Virtex-5 XC5VLX-110T FPGA. For performance evaluation, the handwritten digit recognition application with MNIST database is performed, which reported the best recognition rate of 97.20% when using a neural network architecture of size 784-40-40-10 with two hidden layers, occupying 91.8% FPGA hardware resource. Experimental results show that the proposed neural network architecture is a very promising design choice for high-performance embedded recognition applications.