A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel

In this chapter an overview of phase lock loop is presented, starting with a short review of the history of the PLL in Sect. 1.2. In the following section, Sect. 1.3, various applications of a PLL are discussed. In Sect. 1.4, we discuss the implementation of PLL in communication centric applications. The continued progress in increasing performance, speed, reliability, and the simultaneous reduction in size and cost of integrated circuits (LSI and VLSI) has resulted in a strong interest in the implementation of the phase-locked loop (PLL) in the digital domain. In Sect. 1.5, we give a brief review of the digital version of PLL. Finally, the chapter ends with a note on the organization of this monograph.

The transmission over a wireless channel is restricted to a certain range of frequencies around the some central carrier frequency. The wire is a low-pass filter and hence the carrier frequency for the wireline channel is \(f_c= 0\). This restriction immediately poses some questions about the design of the wireless communication systems. The foremost question is how is reliable communication related to the carrier frequency? Is the communication strategy and hence the transmitter–receiver design particular to the specific carrier frequency? Do we have to design the system based on \(f_c\)? It turns out that we can always work in with the baseband signal (i.e., the signal with \(f_c = 0\)) even for the wireless communication and then convert the baseband signal into the passband signal (a signal that is centered around some nonzero carrier frequency) with the desired carrier frequency. This makes the design of the transmitter and receiver transparent to the carrier frequency. Thus, only the front end of the system needs to be changed if we change \(f_c\). Also, since the bandwidth of the signal \(W\) (typically in KHz) is smaller than the carrier frequency \(f_c\) (typically in MHz), the design of DAC and ADC becomes much easier and modular. The focus of this chapter is on the conversion of the baseband signal to the passband signal and vice versa.

Electrical communication transmitter and receiver techniques strive toward obtaining reliable communication at low cost, with maximum utilization of the channel resources. The information transmitted by the source is received by the destination via a physical medium called a channel. This physical medium, which may be wired or wireless, introduces distortion, noise, and interference in the transmitted information bearing signal. To counteract these effects is one of the requirements while designing a transmitter and receiver end technique. The other requirements are power and bandwidth efficiency at low implementation complexity.

PLL is one of the most commonly used circuits in communicationl engineering. An incomplete list of specific tasks accomplished by PLLs include carrier recovery, clock recovery, tracking filters, frequency and phase demodulation, phase modulation, frequency synthesis, and clock synchronization. PLLs find themselves into a huge set of applications, from radio and television, to virtually every type of communications (wireless, telecom, datacom), to virtually all types of storage device, to noise cancellers, and the like. With the widespread use by the public of such devices, one can claim that PLLs are the most ubiquitous form of feedback system built by engineers. This chapter discusses the basic operational principles of PLL. The mathematical models of the various components of PLL are discussed. Both linear and nonlinear model of PLL are explored. Finally, the chapter ends with a representation of PLL in S-domain.

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated because the usable voltage ranges are decreasing with every new integration step. The continued progress in increasing performance, speed, reliability, and the simultaneous reduction in size and cost of integrated circuits (LSI and VLSI) has resulted in a strong interest in implementation of the phase-locked loop (PLL) in the digital domain. In this chapter an overview of the Digital Phase-Locked-Loop (DPLL) system architecture is presented. An introduction to the operation is given, considering each of the DPLL components individually. The discrete time mathematical models of the various components of DPLL are discussed. Finally, the chapter ends with notes on classification of DPLL based on phase detection techniques, operational principles of various types of phase detector are also discussed.

The coherent detection of a digitally modulated signal requires that the transmitter and the receiver are synchronized to each other. Synchronization is an important requirement in the context of digital communications systems, where several levels of synchronization must be established before data recovery can take place successfully. We provide here a simple overview of various techniques applicable to the task of synchronization in this chapter. It includes an overview of some traditional methods of carrier and timing synchronization, often based on analog electronic circuit realizations, and carries on to introduce timing synchronization structures, sampling schemes, and timing error detectors more suited to contemporary implementations of all-digital receivers.

The structure of a Digital Phase-Locked Loop (DPLL)-based systems for dealing with Nakagami-m fading is proposed in this chapter. The emphasis of the work is the implementation of the essential components of a DPLL for better reception of signals with certain modulation transmitted through Nakagami-m channels. A sixth order polynomial fitting algorithm for better phase-frequency detection has been implemented, which has helped to attain optimum performance of DPLL. The results of simulation of the proposed DPLL with Nakagami-m fading and QPSK modulation shows that the proposed method provides better performance than existing systems of similar type.

The modified structure of a Least Square Polynomial Fitting Filter-based Digital Phase-Locked Loop-based systems for dealing with Nakagami-m fading is proposed here. The emphasis of the work is the implementation of the essential components of a DPLL for better reception of signals with certain modulation transmitted through Nakagami-m channels. A sixth order Least Square Polynomial Fitting (LSPF) block and Roots Approximator (RA) for better phase-frequency detection has been implemented as a replacement of Phase Frequency Detector (PFD) and Loop Filter (LF) of a traditional DPLL, which has helped to attain optimum performance of DPLL. The results of simulation of the proposed DPLL with Nakagami-m fading and QPSK modulation show that the proposed method provides better performance than existing systems of similar type.

The modified structure of Digital Phase-Locked Loop (DPLL)-based systems for dealing with Nakagami-m fading is proposed here. The emphasis of the work is to generate input signal under various fading conditions with certain modulation transmitted through Nakagami-m channels and to evaluate the performance of the proposed DPLL in terms of Bit Error Rate (BER). Statistical characteristics of the faded input signal ar evaluated in terms of Probability Distribution Function (PDF), Level Crossing Rate (LCR) and Average Fade Duration (AFD). A sixth order Least Square Polynomial Fitting (LSPF) block and Roots Approximator (RA) for better phase-frequency detection is implemented as a replacement for Phase Frequency Detector (PFD) and Loop Filter (LF) of a traditional DPLL, which has helped to attain optimum performance of DPLL. The results of simulation of the proposed DPLL with Nakagami-m fading and QPSK modulation show that the proposed method provides better performance than existing systems of similar type.

Carrier and symbol recovery in severely faded Nakagami-m channel is a challenging area. It requires design of certain systems that can capture the carrier and symbols during the reception process. There are several known approaches [1‐3] but very few report the use of Phase-Locked Loop (PLL)-based methods [4‐7]. Here, in this chapter, we propose a Digital Phase-Locked Loop (DPLL)-based system for carrier and symbol recovery in severely faded Nakagami-m channel. We report the performance of the proposed system in terms of Symbol Error Probability (SEP) while recovering carrier and symbols from QPSK-modulated signals in presence of phase error. SEP performance of the DPLL is compared for cases of uncoded and BCH (15, 7) coded conditions. Results shows that the SEP performance improves significantly on application of BCH (15, 7)-based error detection and correction mechanism when used with the DPLL-based system.

In this chapter the design of a digital receiver for carrier phase tracking is presented. The receiver architecture includes a Least Square Polynomial Fitting (LSPF)-based Digital Phase Locked Loop (DPLL). Bit Error Rate (BER) performance of the proposed system for dealing with Rayleigh and Rician fading for different numbers of paths with coded and uncoded channel is presented here. The performance of the DPLL for carrier phase tracking with signal using QPSK modulation transmitted through Rayleigh and Rician fading channels is compared with coded and uncoded conditions. Simulation results show that the proposed DPLL-based approach shows significant improvement using BCH coding both in Rayleigh and Rician fading channels. Several essential processes like noise and CCI cancellation, equalization, etc., that are integral to the traditional frameworks are made redundant by the proposed DPLL-based approach.The composite outcome of these separate processes is combined by the DPLL action making it a reliable and efficient mechanism leading to a compact design.

In this chapter, the structure of a Squaring Loop-based Digital Phase-Locked Loop (DPLL) for carrier detection over multipath Nakagami channel is presented. The emphasis of the work is the implementation of the essential components of a Squaring Loop for better carrier synchronization to the received signal with certain modulation transmitted through Nakagami channels. A Zero-Crossing algorithm-based phase-frequency detection technique is implemented, which has helped to attain optimum performance of the loop. The results of simulation of the proposed DPLL with Nakagami fading and BPSK modulation show that the proposed method provides efficient carrier synchronization despite signal being corrupted under severely faded condition

Consumers demand more from their technology. Whether it is a television, cellular phone, or refrigerator, the latest technology purchase must have new features. With the advent of the Internet, the most-wanted feature is better, faster access to information. Cellular subscribers pay extra on top of their basic bills for such features as instant messaging, stock quotes, and even Internet access right on their phones. To support such a powerful system, we need pervasive, high-speed wireless connectivity. A number of technologies currently exist to provide users with high-speed digital wireless connectivity; Bluetooth and 802.11 are examples. These two standards provide very high-speed network connections over short distances, typically in tens of meters. The goal is the same: long-range, high-speed wireless, which for the purposes of this chapter will be called 4G, for fourth-generation wireless system. Fourth-generation wireless needs to be standardized due to its enticing advantages to both users and providers. Each generation is characterized by new frequency bands, higher data rates and non-backwards compatible transmission technology. The first release of the 3GPP Long-Term Evolution (LTE) standard does not completely fulfill the ITU 4G requirements called IMT-Advanced. First release LTE is not backwards compatible with 3G, but is a pre-4G or 3.9G technology, however, sometimes branded “4G” by the service providers. Its evolution LTE Advanced is a 4G technology. WiMAX is another technology verging on or marketed as 4G.