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Journal of Electronic Testing

Erschienen in:

10.12.2021

A Framework for Configurable Joint-Scan Design-for-Test Architecture

verfasst von: Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh

Erschienen in: Journal of Electronic Testing | Ausgabe 5-6/2021

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Abstract

Test time, test data volume, and test power have been a major concern in Serial Access Scan (SAS) based manufacturing test. Alternatively, the Random Access Scan (RAS) architecture has been proposed to mitigate some of these problems. However, some of the drawbacks, particularly the area and routing congestion of RAS puts a limit on its industry adoption. In this work, we propose a framework of a new scan architecture which we name as Joint-scan that aims to combine both the SAS and RAS to harness the best out of each of the architectures. The principle is to harness the advantage of the area from SAS architecture and the advantage of test power from RAS architecture. The other two parameters, test time and test data volume, are minimized by fine-tuning the proposed scan architecture. The architecture is also configurable to take the design constraints into consideration. Effectiveness of the architecture is experimentally demonstrated on the scaled ISCAS 89 circuits.

Vorheriger Artikel On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization

Nächster Artikel Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations

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Titel: A Framework for Configurable Joint-Scan Design-for-Test Architecture
verfasst von: Jaynarayan T. Tudu
Satyadev Ahlawat
Sonali Shukla
Virendra Singh
Publikationsdatum: 10.12.2021
Verlag: Springer US
Erschienen in: Journal of Electronic Testing / Ausgabe 5-6/2021
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-021-05978-6

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