Skip to main content
Erschienen in: Journal of Computational Electronics 3/2020

18.04.2020

A genetic algorithm to optimize the performance of the tunneling field-effect transistor

verfasst von: Muhammad Elgamal

Erschienen in: Journal of Computational Electronics | Ausgabe 3/2020

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The double-gate tunneling field-effect transistor (DGTFET) is investigated with two channel lengths (50 and 20 nm), along with the effect of the variation of the device design on its overall direct-current (DC) and radiofrequency (RF) performance. The studied design parameters are the drain doping abruptness (or spread) and its shift relative to the gate electrode. Additionally, the gate work function, and the dielectric material and its thickness are investigated. The studied performance parameters are the ON/OFF ratio, the maximum cutoff frequency, the subthreshold swing, and the ambipolar current. The device’s figure of merit (FOM) is expressed as a weighted-sum objective function for optimization by a genetic algorithm (GA). The results are validated against multifactorial experimentation to study the effect of changing each parameter on the FOM. It is shown that the genetic optimization can enhance the performance of the 20-nm-channel device to become comparable to that of a device with a long channel of 50 nm. The GA is run multiple times using parallel processing, MATLAB, and a technology computer-aided design (TCAD) model to validate its efficiency for the optimization of electronic devices when a TCAD model can be built without a great need to define a mathematical model in closed form.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Seabaugh, A., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic, ieeexplore.ieee.org (2010) Seabaugh, A., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic, ieeexplore.ieee.org (2010)
2.
Zurück zum Zitat Verhulst, A., et al.: Si-based tunnel field-effect transistors for low-power nano-electronics, ieeexplore.ieee.org (2011) Verhulst, A., et al.: Si-based tunnel field-effect transistors for low-power nano-electronics, ieeexplore.ieee.org (2011)
3.
Zurück zum Zitat Morris, D.H., Avci, U.E., Rios, R., Young, I.A.: Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics. IEEE J. Emerg. Sel. Top. Circuits Syst. 4(4), 380–388 (2014)CrossRef Morris, D.H., Avci, U.E., Rios, R., Young, I.A.: Design of low voltage tunneling-FET logic circuits considering asymmetric conduction characteristics. IEEE J. Emerg. Sel. Top. Circuits Syst. 4(4), 380–388 (2014)CrossRef
4.
Zurück zum Zitat Strangio, S., et al.: Digital and analog TFET circuits: design and benchmark. Solid-State Electron. 146, 50–65 (2018)CrossRef Strangio, S., et al.: Digital and analog TFET circuits: design and benchmark. Solid-State Electron. 146, 50–65 (2018)CrossRef
5.
Zurück zum Zitat Anand, S., Sarin, R.K.: Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform. Superlattices Microstruct. 97, 60–69 (2016)CrossRef Anand, S., Sarin, R.K.: Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform. Superlattices Microstruct. 97, 60–69 (2016)CrossRef
6.
Zurück zum Zitat Saurabh, S., Kumar, M.J.: Fundamentals of Tunnel Field-Effect Transistors. CRC Press (2016) Saurabh, S., Kumar, M.J.: Fundamentals of Tunnel Field-Effect Transistors. CRC Press (2016)
7.
Zurück zum Zitat Lu, H., Seabaugh, A.: Tunnel field-effect transistors: state-of-the-art. IEEE J. Electron Devices Soc. 2(4), 44–49 (2014)CrossRef Lu, H., Seabaugh, A.: Tunnel field-effect transistors: state-of-the-art. IEEE J. Electron Devices Soc. 2(4), 44–49 (2014)CrossRef
8.
Zurück zum Zitat Boucart, K., et al.: Double-gate tunnel FET with high-gate dielectric, ieeexplore.ieee.org (2007) Boucart, K., et al.: Double-gate tunnel FET with high-gate dielectric, ieeexplore.ieee.org (2007)
9.
Zurück zum Zitat Toh, E.H., Wang, G.H., Samudra, G., Yeo, Y.C.: Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization. Appl. Phys. Lett. 90(26), 263507 (2007)CrossRef Toh, E.H., Wang, G.H., Samudra, G., Yeo, Y.C.: Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization. Appl. Phys. Lett. 90(26), 263507 (2007)CrossRef
10.
Zurück zum Zitat Liang, R., Cui, N., Zhao, M., Wang, J., Xu, J.: High performance tunnel field effect transistor with a tri-material-gate structure. In: 2011 International Semiconductor Device Research Symposium, ISDRS 2011 (2011) Liang, R., Cui, N., Zhao, M., Wang, J., Xu, J.: High performance tunnel field effect transistor with a tri-material-gate structure. In: 2011 International Semiconductor Device Research Symposium, ISDRS 2011 (2011)
13.
Zurück zum Zitat Elgamal, M., Sinjab, A., Fedawy, M., Shaker, A.: Effect of doping profile and the work function variation on performance of double-gate TFET. Int. J. Integr. Eng. 11, 365–370 (2019)CrossRef Elgamal, M., Sinjab, A., Fedawy, M., Shaker, A.: Effect of doping profile and the work function variation on performance of double-gate TFET. Int. J. Integr. Eng. 11, 365–370 (2019)CrossRef
14.
Zurück zum Zitat Loh, W., Jeon, K., Kang, C., Oh, J., et al.: Sub-60 nm Si tunnel field effect transistors with Ion 100 µA µm.pdf, ieeexplore.ieee.org (2010) Loh, W., Jeon, K., Kang, C., Oh, J., et al.: Sub-60 nm Si tunnel field effect transistors with Ion 100 µA µm.pdf, ieeexplore.ieee.org (2010)
15.
Zurück zum Zitat Jhaveri, R., Nagavarapu, V., Woo, J.C.S.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58, 80–86 (2011)CrossRef Jhaveri, R., Nagavarapu, V., Woo, J.C.S.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58, 80–86 (2011)CrossRef
16.
Zurück zum Zitat Affenzeller, M., Wagner, S., Winkler, S., Beham, A.: Genetic Algorithms and Genetic Programming: Modern Concepts and Practical Applications. Crc Press (2009) Affenzeller, M., Wagner, S., Winkler, S., Beham, A.: Genetic Algorithms and Genetic Programming: Modern Concepts and Practical Applications. Crc Press (2009)
17.
Zurück zum Zitat Utsler, J.: Genetic Algorithm Based Optimization of Advanced Solar Cell Designs Modeled in Silvaco AtlasTM. Naval Postgraduate School, Monterey (2006) Utsler, J.: Genetic Algorithm Based Optimization of Advanced Solar Cell Designs Modeled in Silvaco AtlasTM. Naval Postgraduate School, Monterey (2006)
18.
Zurück zum Zitat Alì, G., Butera, F., Rotundo, N.: Geometrical and physical optimization of a photovoltaic cell by means of a genetic algorithm. J. Comput. Electron. 13(1), 323–328 (2014)CrossRef Alì, G., Butera, F., Rotundo, N.: Geometrical and physical optimization of a photovoltaic cell by means of a genetic algorithm. J. Comput. Electron. 13(1), 323–328 (2014)CrossRef
19.
Zurück zum Zitat Chen, M.J., Wu, C.Y.: A new method for computer-aided optimization of solar cell structure. Solid-State Electron. 28(8), 751–761 (1985)CrossRef Chen, M.J., Wu, C.Y.: A new method for computer-aided optimization of solar cell structure. Solid-State Electron. 28(8), 751–761 (1985)CrossRef
20.
Zurück zum Zitat Chen, Y., Lee, C., et al.: Calculation of the optimum installation angle for fixed solar-cell panels based on the genetic algorithm and the simulated-annealing method, ieeexplore.ieee.org (2005) Chen, Y., Lee, C., et al.: Calculation of the optimum installation angle for fixed solar-cell panels based on the genetic algorithm and the simulated-annealing method, ieeexplore.ieee.org (2005)
21.
Zurück zum Zitat Jervase, J.A., Bourdoucen, H., Al-Lawati, A.: Solar cell parameter extraction using genetic algorithms. Meas. Sci. Technol. 12(11), 1922–1925 (2001)CrossRef Jervase, J.A., Bourdoucen, H., Al-Lawati, A.: Solar cell parameter extraction using genetic algorithms. Meas. Sci. Technol. 12(11), 1922–1925 (2001)CrossRef
22.
Zurück zum Zitat ATLAS User’s Manual: Software, Device Simulation, vol. 2, no. November. Santa Clara (1998) ATLAS User’s Manual: Software, Device Simulation, vol. 2, no. November. Santa Clara (1998)
23.
Zurück zum Zitat Montgomery, D.: Design and Analysis of Experiments. John wiley & Sons (2017) Montgomery, D.: Design and Analysis of Experiments. John wiley & Sons (2017)
24.
Zurück zum Zitat Shaker, A., ElSabbagh, M., et al.: Impact of nonuniform Gate Oxide Shape on TFET Performance: A Reliability Issue. Elsevier, Amsterdam (2019) Shaker, A., ElSabbagh, M., et al.: Impact of nonuniform Gate Oxide Shape on TFET Performance: A Reliability Issue. Elsevier, Amsterdam (2019)
25.
Zurück zum Zitat Chaturvedi, P., Kumar, M.J.: Impact of gate leakage considerations in tunnel field effect transistor design. Jpn. J. Appl. Phys. 53(7), 074201 (2014)CrossRef Chaturvedi, P., Kumar, M.J.: Impact of gate leakage considerations in tunnel field effect transistor design. Jpn. J. Appl. Phys. 53(7), 074201 (2014)CrossRef
26.
Zurück zum Zitat Elgamal, M.: The effect of source and drain pocketing on the performance of double-gate tunnelling field-effect transistor. J. Phys. Conf. Ser. (2019) Elgamal, M.: The effect of source and drain pocketing on the performance of double-gate tunnelling field-effect transistor. J. Phys. Conf. Ser. (2019)
27.
Zurück zum Zitat Elgamal, M., Fedawy, M.: Optimizing gate-on-source overlapped TFET device parameters by changing gate differential work function and overlap dielectric. In: Proceedings of 2019 International Conference on Innovative Trends in Computer Engineering, ITCE 2019, pp. 347–352 (2019) Elgamal, M., Fedawy, M.: Optimizing gate-on-source overlapped TFET device parameters by changing gate differential work function and overlap dielectric. In: Proceedings of 2019 International Conference on Innovative Trends in Computer Engineering, ITCE 2019, pp. 347–352 (2019)
28.
Zurück zum Zitat Affenzeller, M., Winkler, S., Wagner, S., Beham, A.: Genetic Algorithms and Genetic Programming: Modern Concepts and Practical Applications. Crc Press (2009) Affenzeller, M., Winkler, S., Wagner, S., Beham, A.: Genetic Algorithms and Genetic Programming: Modern Concepts and Practical Applications. Crc Press (2009)
30.
Zurück zum Zitat Baeck, T., Fogel, D., Michalewicz, Z., Fogel, D., Michalewicz, Z.: Handbook of Evolutionary Computation. CRC Press, New York (1997)CrossRef Baeck, T., Fogel, D., Michalewicz, Z., Fogel, D., Michalewicz, Z.: Handbook of Evolutionary Computation. CRC Press, New York (1997)CrossRef
Metadaten
Titel
A genetic algorithm to optimize the performance of the tunneling field-effect transistor
verfasst von
Muhammad Elgamal
Publikationsdatum
18.04.2020
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 3/2020
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-020-01492-8

Weitere Artikel der Ausgabe 3/2020

Journal of Computational Electronics 3/2020 Zur Ausgabe

Neuer Inhalt