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2013 | OriginalPaper | Buchkapitel

A Hardware Design for Binary Image Recognition

verfasst von : Saul Martinez-Diaz

Erschienen in: IAENG Transactions on Engineering Technologies

Verlag: Springer Netherlands

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Abstract

Recently, nonlinear composite correlation filters have been proposed for distortion-invariant pattern recognition. The filter design is based on logical operations and the correlation is computed with a nonlinear operation called morphological correlation. In this paper a new implementation in parallel hardware of these kinds of filters for image recognition is proposed. The architecture is designed for a Field Programmable Gate Array (FPGA) device. The proposed design performs the most time consuming task of the recognition procedure. In consequence, it reduces the time required for the nonlinear operations in the spatial domain. Simulation results are provided and discussed.

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Metadaten
Titel
A Hardware Design for Binary Image Recognition
verfasst von
Saul Martinez-Diaz
Copyright-Jahr
2013
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-94-007-6190-2_37

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