A Harris Corner Detector Implementation in SoC-FPGA for Visual SLAM

The present paper discusses the implementation of the Harris and Stephen corner detector algorithm optimized for an embedded system-on-a-chip (SOC) platform that integrates a multicore ARM processor and FPGA fabric in a single chip, the Xilinx Zynq-7000. The algorithm is implemented as a hardware co-processor on the FPGA portion of the SoC. As a whole, the SoC is used as a stereo vision pre-processing module to retrieve depth information from the features in order to compose 3D landmark points for Visual SLAM, speeding up feature extraction and relieving this highly parallelizable process from the main embedded processor. The optimizations of the algorithm’s hardware implementation take into account the particularities of the SoC, such as compliance with its I/O requirements and FPGA’s constraints on the amount of logical elements available for hardware synthesis. Also, optimizations done in order to reduce the time of execution of the algorithm in hardware, such as parallelization and introduction of a pipeline, are also presented in the article. A speedup of 1.77 was achieved when comparing the time of execution of the algorithm in the hardware coprocessor with the algorithm running in software in the dual-core ARM processor.