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Über dieses Buch

This Open Access book celebrates Professor Peter Marwedel's outstanding achievements in compilers, embedded systems, and cyber-physical systems. The contributions in the book summarize the content of invited lectures given at the workshop “Embedded Systems” held at the Technical University Dortmund in early July 2019 in honor of Professor Marwedel's seventieth birthday.

Provides a comprehensive view from leading researchers with respect to the past, present, and future of the design of embedded and cyber-physical systems;Discusses challenges and (potential) solutions from theoreticians and practitioners on modeling, design, analysis, and optimization for embedded and cyber-physical systems;Includes coverage of model verification, communication, software runtime systems, operating systems and real-time computing.

Inhaltsverzeichnis

Frontmatter

Open Access

Chapter 1. Peter Marwedel and the Department of Computer Science of the TU Dortmund University

Abstract
A seventieth birthday is an appropriate occasion to look back on the life path so far. In the following, this is done for Professor Peter Marwedel from the perspective of the Department of Computer Science of TU Dortmund University, where he spent the essential time of his professional life.
Gernot Fink, Heinrich Müller

Open Access

Chapter 2. Testing Implementation Soundness of a WCET Analysis Tool

Abstract
We have developed and implemented the only widely used sound WCET analysis technology. The claim of soundness is a strong one, given the many necessary component techniques of WCET analysis and the need to incorporate an abstraction of the execution platform. This article deals with the qualification of the AbsInt timing-analysis tool, aiT, as required by several international standards for safety-critical software. We briefly sketch these requirements, give a short description of our timing-analysis method, and then concentrate on the most complex part, the microarchitectural analysis. This analysis phase uses an abstraction of the execution platform. To arrive at this abstraction is a complex, error-prone process. The main focus of the article is the technique to validate the abstract execution platform by trace validation.
Reinhard Wilhelm, Markus Pister, Gernot Gebhard, Daniel Kästner

Open Access

Chapter 3. The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Abstract
Current and emerging embedded applications require ever larger amount of data that have to be processed. Due to their large size, this data has to be stored off-chip in dynamic random access memories (DRAMs). The challenges introduced by DRAMs in those systems are manifold. These include limited bandwidth and latency, as well as power consumption and reduced reliability due to technology scaling. In this chapter we highlight the major challenges and possible solutions for the integration of DRAM subsystems into embedded computing systems.
Matthias Jung, Christian Weis, Norbert Wehn

Open Access

Chapter 4. On the Formalism and Properties of Timing Analyses in Real-Time Embedded Systems

Abstract
Real-time embedded systems are information processing systems that require both functional and timing correctness.
Such systems usually interact with the physical world, where time naturally processes. Therefore, safe bounds of deterministic or probabilistic timing properties are required. Existing analyses and optimizations for scheduling algorithms and resource management policies in complex real-time systems are usually ad hoc solutions for a specific studied problem. In this chapter, we challenge this design and analytical practice, since the future design of real-time systems will be more complex, not only in the execution model but also in the parallelization, communication, and synchronization models. We strongly believe that the future design of real-time systems requires formal properties that can be used modularly to compose safe and tight analysis as well as optimization for the scheduler design and schedulability test problems. This chapter summarizes our recent progress at TU Dortmund in this regard with respect to both deterministic and probabilistic properties.
Jian-Jia Chen, Wen-Hung Huang, Georg von der Brüggen, Kuan-Hsun Chen, Niklas Ueter

Open Access

Chapter 5. ASSISTECH: An Accidental Journey into Assistive Technology

Abstract
ASSISTECH is an inter-disciplinary laboratory located in Amar Nath Sashi Khosla School of Information Technology and is born out of the initial work of faculty and students in Department of Computer Science and Engineering. ASSISTECH has achieved some success in its 12 +  years of existence in not only designing affordable products and solutions for mobility and education of visually impaired but also in building an ecosystem of translational research and dissemination to reach the end users. It is not a journey of any major technological breakthrough but of perseverance in creating an ecosystem for delivery and reaching out and connecting to people with passion to make a difference in this domain. In this article I have tried to capture this unusual journey of direct societal connect and impact—not very common in an academic Institution.
M. Balakrishnan

Open Access

Chapter 6. Reflecting on Self-Aware Systems-on-Chip

Abstract
In this chapter, we explore adaptive resource management techniques for cyber-physical systems-on-chip that employ principles of computational self-awareness to varying degrees, specifically reflection. By supporting various self-X properties, systems gain the ability to reason about runtime configuration decisions by considering the significance of competing objectives, user requirements, and operating conditions, while executing unpredictable workloads.
Bryan Donyanavard, Tiago Mück, Kasra Moazzemi, Biswadip Maity, Caio Batista de Melo, Kenneth Stewart, Saehanseul Yi, Amir M. Rahmani, Nikil Dutt

Open Access

Chapter 7. Pushing the Limits of Parallel Discrete Event Simulation for SystemC

Abstract
The IEEE SystemC language is widely used in industry and academia to model and simulate system-level designs. Despite the availability of multi- and many-core host processors, however, the Accellera reference simulator is still based on sequential discrete event simulation, utilizing only a single core at any time. While many advanced parallel simulation approaches have been proposed, most require modification of the SystemC source code so that the model is free from parallel access conflicts and rely on the designer to manually perform this difficult transformation.
The Recoding Infrastructure for SystemC (RISC) project addresses the parallel SystemC simulation problem with automatic compiler-based analysis and source code transformation. A dedicated SystemC compiler and corresponding parallel simulator provide safe static analysis and recoding, and thus automatically achieve fast parallel simulation of SystemC models.
We share the RISC framework as open source in order to enable easy evaluation, foster collaboration, and further extend our proof-of-concept implementation.
Rainer Dömer, Zhongqi Cheng, Daniel Mendoza, Emad Arasteh

Open Access

Chapter 8. Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems

Abstract
Negative capacitance field-effect transistor (NCFET) is one of the very promising emerging technologies that may replace existing CMOS technology in the future. This is due to its ability to push the sub-threshold swing of transistors to below 60 mV/decade, which what fundamentally limits voltage scaling in conventional CMOS technology and what has led in the past to the discontinuation of Dennard’s scaling. In this chapter, we demonstrate how NCFET technology can reshape the future of many-core systems—especially when it comes to thermally constrained processors. Compared to conventional CMOS technology, NCFET technology allows processors (1) to be clocked at higher frequency without any increase in the power density or (2) to operate at lower voltages, without sacrificing performance requirements. The latter leads to a significant power saving that plays a major role in increasing the total number of processor cores that can be simultaneously powered on without exceeding the predetermined thermal constraints. In addition, we demonstrate how NCFET technology makes the leakage power in processors increase, instead of decrease as in conventional CMOS technology, when voltage is scaled down. This fundamentally breaks down the core assumption of all existing power management techniques. Hence, novel runtime power management techniques need to be devolved in which such a new inverse leakage-voltage dependency is carefully considered. Otherwise, the efficiency of NCFET-based processors cannot be optimized. In this chapter, we also demonstrate the first NCFET-aware dynamic voltage scaling that optimizes the power of processor while taking the inverse leakage-voltage dependency into account.
Hussam Amrouch, Martin Rapp, Sami Salamin, Jörg Henkel

Open Access

Chapter 9. Run-Time Enforcement of Non-functional Program Properties on MPSoCs

Abstract
For many embedded applications, non-functional requirements, e.g., execution time, must be guaranteed in tight bounds. Unfortunately, many applications, e.g., video streaming, exhibit high variability in, e.g., per-iteration execution time, especially on MPSoC platforms. Such jitters are partly imposed by the system management software practicing, e.g., cache strategies and power management, and partly imposed by workload variation, e.g., the number of objects in an input image. In this paper, we classify and present techniques for enforcement of non-functional properties. These techniques make the system management software become the application’s advocate instead of both acting independently. For the example of enforcement of execution time intervals, we present centralized and distributed enforcement techniques in which preferential threads called e-lets are generated to control system resources in view of application/task workload variation. The behavior of each e-let is formally specified by an enforcement automaton, derived based on a static application characterization. We consider a case study on timing enforcement of image processing applications on MPSoCs with per-core DVFS and present a DSE to construct per-task enforcement automata with provably minimal energy consumption which, in our case study, enables 41 % energy savings.
Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann

Open Access

Chapter 10. Compilation for Real-Time Systems a Decade After Predator

Abstract
On the occasion of Peter Marwedel’s 70th anniversary, this article provides a survey over a decade of research in the field of compiler techniques for real-time systems. Ten years ago, during the EU-funded project Predator, it was him who led the work package on compilers. As will be shown in this survey, the work done in this domain had such a fundamental character that it laid the ground for follow-up research that lasts since the end of Predator until today. This article particularly emphasizes results achieved in the challenging areas of scheduling-aware optimization of multi-task systems, of analysis and optimization of Multi-Processor Systems on Chip, and of predictable multi-objective optimizations.
Heiko Falk, Shashank Jadhav, Arno Luppold, Kateryna Muts, Dominic Oehlert, Nina Piontek, Mikko Roth

Backmatter

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