Offline and online built-in self-test (BIST) designs are low-cost platforms to test very complex modern chips. The offline BIST design embeds the test pattern generator (TPG) into the chip to be activated in the test time. On the other hand, the online (or concurrent) BIST design eliminates the TPG and utilizes the system’s input vectors to accomplish the test process. This paper proposes a BIST design that supports both online and offline tests. In the online part of the design, a selector module passes the input vectors which belong to a pre-computed test set to the reduction part. The test set contains the test vectors, which generate 0 remainders in the division by the LFSR’s polynomial of the selector. In the concurrent test latency (CTL) aware design, the size of the test set is expanded by adopting the selecting part to select the test vectors which generate the same remainders in the division by two different polynomials. The internal TPG of the offline part is realized based on the HW-aware test set using the shifted versions of LFSR’s polynomial and XORing their contents. The reduction part compresses the widths of the current test vector and the related CUT outputs. The compactor LFSR compresses the test vectors so that the resulted remainders would be different for all test vectors to solve the masking problem. The small size of the test set and the compacting test vectors resulted in a tremendous reduction of hardware overhead. The proposed method imposes less than 6% and 28% hardware overhead for large size and very large size circuits, respectively. The simulation results for ISCAS 85, ISCAS 89, and ITC99 benchmark circuits showed that our proposed BIST design outperforms the previous state-of-the-art in both hardware overheads. Furthermore, the CTL reduces 100 times by the proposed CTL-aware approach on average.
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