Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben
Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 2/2021

14.04.2021

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs

Erschienen in: Journal of Electronic Testing | Ausgabe 2/2021

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Through Silicon Vias (TSVs) are crucial elements for the reliable operation and yield of three dimensional integrated circuits (3D ICs). Defects are a serious concern in TSV structures. A post-bond, parallel testing and diagnosis scheme is proposed in this work, for the detection and location of resistive open or short to substrate defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing method provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical model simulations and Monte-Carlo analysis results, using the 65 nm technology of TSMC, prove the effectiveness of the new method. Additionally, two representative methods from the literature are simulated and compared to the proposed one, in terms of effectiveness, robustness, tolerance, cost and design for testability effort. The proposed scheme is proven to perform better based on all presented criteria.
Vorheriger Artikel Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality
Nächster Artikel A Cascaded Multicasting Architecture for Test Data Compression

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Jetzt informieren
Weitere Produktempfehlungen anzeigen
Literatur
1.
Fang X, Yu Y, Peng X (2019) "TSV Prebond Test Method Based on Switched Capacitors," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(1):205–218
2.
Hsu W, Kochte MA, Lee K (2017) Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. IEEE Trans Comput Aided Des Integr Circuits Syst 36(6):1004–1017CrossRef
3.
Huang Y, Pan C, Lin S, Guo M (2018) Machine-Learning Approach in Detection and Classification for Defects in TSV-Based 3-D IC. IEEE Transactions on Components, Packaging and Manufacturing Technology 8(4):699–706CrossRef
4.
"International Technology Roadmap for Semiconductors" (2013)
5.
Jang J, Cheong M, Kang S (2019) TSV Repair Architecture for Clustered Faults. IEEE Trans Comput Aided Des Integr Circuits Syst 38(1):190–194CrossRef
6.
Kannan S, Kim B, Ahn B (2012) "Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects". J Electron Test 28, 39–51
7.
Katti G, Stucchi M, De Meyer K, Dehaene W (2010) Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs. IEEE Trans Electron Devices 57(1):256–262CrossRef
8.
Kim J, Cho J, Kim J, Yook J-M, Kim JC, Lee J, Park K, Pak JS (2014) High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via. IEEE Transactions on Components, Packaging and Manufacturing Technology 4(4):697–707CrossRef
9.
Koneru A, Kannan S, Chakrabarty K (2017) Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits. ACM Journal on Emerging Technologies in Computing Systems (JETC) 13(4):1–23CrossRef
10.
Lee Y, Kim J, Choi I, Kang S (2016) "A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs,". Proc. International SoC Design Conference (ISOCC), Jeju, 129–130
11.
Lee Y, Lim H, Kang S (2017) Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. IEEE Trans Comput Aided Des Integr Circuits Syst 36(10):1759–1763CrossRef
12.
Lou Y, Yan Z, Zhang F et al (2012) Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods. J Electron Test 28:27–38CrossRef
13.
Maity DK, Roy SK, Giri C (2018) "Identification of Faulty TSVs in 3D IC During Pre-Bond Testing,". Proc. 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID), Pune, 109–114
14.
Maity D, Roy S, Giri C, Rahaman H (2018) "Identification of Faulty TSV with a Built-In Self-Test Mechanism,". Proc. IEEE 27th Asian Test Symposium (ATS), Hefei, 1–6
15.
Maity DK, Roy SK, Giri C (2019) Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. J Electron Test 35:741–759CrossRef
16.
Metzler C, Todri A, Bosio A, Dilillo L, Girard P, Virazel A (2012) "Through-Silicon-Via resistive-open defect analysis,". Proc. 17th IEEE European Test Symposium (ETS), Annecy, 1–1
17.
Noia B, Chakrabarty K, Marinissen EJ (2012) Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J Electron Test 28:103–120CrossRef
18.
Papadopoulos S, Gerakis V, Tsiatouhas Y, Hatzopoulos A (2017) "Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs,". Proc. 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki , 1–6
19.
Rodríguez-Montañés R, Arumí D, Figueras J (2019) "Postbond Test of Through-Silicon Vias With Resistive Open Defects," in IEEE Transact Very Large Scale Integrat (VLSI) Syst 27(11):2596–2607
20.
Sung H, Cho K, Yoon K, Kang S (2017) "A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories," in IEEE Transact Very Large Scale Integrat (VLSI) Syst 22(11):2380–2387
21.
Ye F, Chakrabarty K (2012) "TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation,". Proc. DAC Design Auto Conference 2012, San Francisco, CA, 1024–1030
22.
You JW, Huang SY, Lin YH, Tsai MH, Kwai DM, Chou YF, Wu CW (2013) "In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis," in IEEE Transact Very Large Scale Integrat (VLSI) Syst, 21:(3):443–453.
23.
Yu Y, Fang X, Peng X (2020) A Post-Bond TSV Test Method Based on RGC Parameters Measurement. IEEE Trans Comput Aided Des Integr Circuits Syst 39(2):506–519CrossRef
24.
Zhang B, Agrawal VD (2017) Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J Electron Test 33:573–589CrossRef
Metadaten
Titel
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs
Publikationsdatum
14.04.2021
Erschienen in
Journal of Electronic Testing / Ausgabe 2/2021
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-021-05939-z

Weitere Artikel der Ausgabe 2/2021

Journal of Electronic Testing 2/2021 Zur Ausgabe

OriginalPaper

A Cascaded Multicasting Architecture for Test Data Compression

OriginalPaper

Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit

EditorialNotes

Editorial

OriginalPaper

Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model

OriginalPaper

Method of Implanting Hardware Trojan Based on EHW in Part of Circuit

OriginalPaper

Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions

Neuer Inhalt

    Bildnachweise