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Journal of Electronic Testing

Erschienen in:

09.04.2022

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design

Erschienen in: Journal of Electronic Testing | Ausgabe 1/2022

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Abstract

As the feature size of integrated circuit decreases, semiconductor devices become more susceptible to Single-Event-Upset (SEU) effect. This paper proposes a radiation hardened latch for Triple-Node-Upset (TNU) tolerance, which can block any triple node upset. Compared with previous radiation hardened TNU Tolerant (TNUT) latches, the proposed Low power-consumption TNUT (LTNUT) latch has the lowest power consumption. When compared with TNU Hardened Latch (TNUHL), TNUT Latch, TNU Completely Tolerant latch (TNUCT), Single-event Multiple-Node Upset Tolerant latch (SMNUT), TNU self-Recoverable Latch (TNURL), Low Cost and TNU-self-Recoverable Latch (LCTNURL) and Quadruple Dual Interlocked Storage Cell (Quadruple-DICE), the proposed LTNUT latch achieves reduction in power consumption by 30.77%, 17.11%, 40%, 20.25%, 20.25%, 27.59% and 64%, respectively. The proposed LTNUT latch achieves reduction in delay by 94.98%, 98.33%, 54.19%, 70.63% and 66.59% when compared with TNUHL, TNUT Latch, SMNUT, TNURL, LCTNURL, respectively, and introduces rise in delay by 3.38% and 5.52%, respectively, when compared with TNUCT and Quadruple-DICE. The proposed LTNUT latch has the lowest power consumption and second smallest delay. The proposed latch is not severely sensitive to temperature and voltage variations.

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Titel: A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design
Publikationsdatum: 09.04.2022
Erschienen in: Journal of Electronic Testing / Ausgabe 1/2022
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-022-05989-x

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