A new ECC implemented by FPGA with favorable combined performance of speed and area for lightweight IoT edge devices

A new algorithm of elliptic curve cryptography (ECC) is proposed with high-radix interleaved multiplication implemented to reduce computational complexity, which in result presenting an effective performance improvement from the traditional radix-2 interleaved multiplication. ECC is one of RSAs, more suitable than others to be employed in IoT devices, since it enjoys particularly the merit of shorter key lengths while keeping well the security level comparable to other RSAs. This work paid the effort to minimize integrally the operation time and the hardware area of an ECC algorithm based on the interleaved modular multiplication. The minimization is achieved via implementing the modular division part with the right-shift binary inverse algorithm to share the same hardware resource with the modular adders and subtractions. Compared to all the other related, best works on ECC, the proposed architecture reduces successfully the operation cycle time by three-quarters to 1.12 mini-sec, while the multiplier hardware requires three-quarters less area of 13.43k LUT, greatly reducing the cost of IoT devices while maintaining favorable processing speed to arrive at the best favorable figure of merit, the product of is and processing time, among past works as 15.04.