Skip to main content
Erschienen in: Journal of Computational Electronics 3/2020

25.04.2020

A novel 2-D analytical model for the electrical characteristics of a gate-all-around heterojunction tunnel field-effect transistor including depletion regions

verfasst von: C. Usha, P. Vimala, T. S. Arun Samuel, M. Karthigai Pandian

Erschienen in: Journal of Computational Electronics | Ausgabe 3/2020

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

A new two-dimensional analytical model is proposed for the electrical attributes of a gate-all-around heterojunction tunnel field-effect transistor, including the potential distribution, lateral and vertical electric fields, drain current, subthreshold swing, and threshold voltage. The potential distribution in the device is obtained by using the two-dimensional (2-D) Poisson equation, including the depletion regions across the source–channel, channel, and drain–channel regions. The drain current of the proposed device is derived by combining parameters such as the band-to-band generation rate, lateral electric field, and channel thickness as well as the shortest tunneling path in Kane’s model. The threshold voltage is obtained from the second derivative of the drain current. The effects of the depletion regions are also included in the model to obtain accurate results. The results are validated against ATLAS technology computer-aided design (TCAD) simulations with the SILVACO tool, revealing excellent agreement.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Kumar, M., Jit, S.: A novel four-terminal ferroelectric tunnel FET for quasi-ideal switch. IEEE Trans. Nanotechnol. 14, 600–602 (2015)CrossRef Kumar, M., Jit, S.: A novel four-terminal ferroelectric tunnel FET for quasi-ideal switch. IEEE Trans. Nanotechnol. 14, 600–602 (2015)CrossRef
2.
Zurück zum Zitat Kumar, M., Jit, S.: Effects of electrostatically doped source/drain and ferroelectric gate oxide on subthreshold swing and impact ionization rate of strained-Si-on-insulator tunnel field-effect transistors. IEEE Trans. Nanotechnol. 14, 597–599 (2015)CrossRef Kumar, M., Jit, S.: Effects of electrostatically doped source/drain and ferroelectric gate oxide on subthreshold swing and impact ionization rate of strained-Si-on-insulator tunnel field-effect transistors. IEEE Trans. Nanotechnol. 14, 597–599 (2015)CrossRef
3.
Zurück zum Zitat Nagavarapu, R., Jhaveri, R., Woo, J.C.S.: The tunnel source (PNPN) n-MOSFET: a novel high-performance transistor. IEEE Trans. Electron Devices 55, 1013–1019 (2008)CrossRef Nagavarapu, R., Jhaveri, R., Woo, J.C.S.: The tunnel source (PNPN) n-MOSFET: a novel high-performance transistor. IEEE Trans. Electron Devices 55, 1013–1019 (2008)CrossRef
4.
Zurück zum Zitat Gholizadeh, M., Hosseini, S.E.: A 2-D analytical model for doublegate tunnel FETs. IEEE Trans. Electron Devices 61, 1494–1500 (2014)CrossRef Gholizadeh, M., Hosseini, S.E.: A 2-D analytical model for doublegate tunnel FETs. IEEE Trans. Electron Devices 61, 1494–1500 (2014)CrossRef
5.
Zurück zum Zitat Kumar, M.J., Janardhanan, S.: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60, 3285–3290 (2013)CrossRef Kumar, M.J., Janardhanan, S.: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60, 3285–3290 (2013)CrossRef
6.
Zurück zum Zitat Saurabh, S., Kumar, M.J.: Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 58, 404–410 (2011)CrossRef Saurabh, S., Kumar, M.J.: Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 58, 404–410 (2011)CrossRef
7.
Zurück zum Zitat Choi, W.Y., Park, B.G., Lee, J.D., Liu, T.J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)CrossRef Choi, W.Y., Park, B.G., Lee, J.D., Liu, T.J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)CrossRef
8.
Zurück zum Zitat Bhuwalka, K.K., Schulze, J., Eisele, I.: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering. IEEE Trans. Electron Devices 52, 909–917 (2005)CrossRef Bhuwalka, K.K., Schulze, J., Eisele, I.: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering. IEEE Trans. Electron Devices 52, 909–917 (2005)CrossRef
9.
Zurück zum Zitat Lee, M., Jeon, Y., Jung, J.C., Koo, S.M., Kim, S.: Feedback and tunneling operations of a p +-i-n+ silicon nanowire field-effect transistor. Nanotechnology 29, 43 (2018) Lee, M., Jeon, Y., Jung, J.C., Koo, S.M., Kim, S.: Feedback and tunneling operations of a p +-i-n+ silicon nanowire field-effect transistor. Nanotechnology 29, 43 (2018)
10.
Zurück zum Zitat Moselund, K.E., Bjork, M.T., Schmid, H., Ghoneim, H., Karg, S., Lortscher, E., Riess, W., Riel, H.: Silicon nanowire tunnel FETs: low-temperature operation and influence of high-gate dielectric. IEEE Trans. Electron Devices 58, 2911–2916 (2011)CrossRef Moselund, K.E., Bjork, M.T., Schmid, H., Ghoneim, H., Karg, S., Lortscher, E., Riess, W., Riel, H.: Silicon nanowire tunnel FETs: low-temperature operation and influence of high-gate dielectric. IEEE Trans. Electron Devices 58, 2911–2916 (2011)CrossRef
11.
Zurück zum Zitat Usha, C., Vimala, P.: A tunneling FET exploiting in various structure and different models: a review. Int. Conf. Innov. Inf. Embedded Commun. Syst. 6, 72–76 (2015) Usha, C., Vimala, P.: A tunneling FET exploiting in various structure and different models: a review. Int. Conf. Innov. Inf. Embedded Commun. Syst. 6, 72–76 (2015)
12.
Zurück zum Zitat Usha, C., Vimala, P.: Analytical drain current model for fully depleted surrounding gate TFET. J. Nano Res. 55, 75–81 (2018)CrossRef Usha, C., Vimala, P.: Analytical drain current model for fully depleted surrounding gate TFET. J. Nano Res. 55, 75–81 (2018)CrossRef
13.
Zurück zum Zitat Lu, H., Seabaugh, A.: Tunnel field-effect transistors: state-of-the-art. IEEE J. Electron Device Soc. 2, 44–49 (2014)CrossRef Lu, H., Seabaugh, A.: Tunnel field-effect transistors: state-of-the-art. IEEE J. Electron Device Soc. 2, 44–49 (2014)CrossRef
14.
Zurück zum Zitat Vishnoi, R., Kumar, M.J.: Compact analytical drain current model of gate-all-around nanowire tunneling FET. IEEE Trans. Electron Devices 61, 2599–2603 (2014)CrossRef Vishnoi, R., Kumar, M.J.: Compact analytical drain current model of gate-all-around nanowire tunneling FET. IEEE Trans. Electron Devices 61, 2599–2603 (2014)CrossRef
15.
Zurück zum Zitat Khaveh, H.R.T., Mohammadi, S.: Potential and drain current modeling of gate-all-around tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans. Electron Devices 63, 5021–5029 (2016)CrossRef Khaveh, H.R.T., Mohammadi, S.: Potential and drain current modeling of gate-all-around tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans. Electron Devices 63, 5021–5029 (2016)CrossRef
16.
Zurück zum Zitat Bagga, N., Dasgupta, S.: Surface potential and drain current analytical model of gate all around triple metal TFET. IEEE Trans. Electron Devices 64, 606–613 (2017)CrossRef Bagga, N., Dasgupta, S.: Surface potential and drain current analytical model of gate all around triple metal TFET. IEEE Trans. Electron Devices 64, 606–613 (2017)CrossRef
17.
Zurück zum Zitat Kumar, S., Singh, K., Goel, E., Singh, B., Kumar, M., Jit, S.: A compact 2-D analytical model for electrical characteristics of double-gate TFETs with SiO2/high-k2 stacked gate-oxide structure. IEEE Trans. Electron Devices 63, 960–968 (2016) Kumar, S., Singh, K., Goel, E., Singh, B., Kumar, M., Jit, S.: A compact 2-D analytical model for electrical characteristics of double-gate TFETs with SiO2/high-k2 stacked gate-oxide structure. IEEE Trans. Electron Devices 63, 960–968 (2016)
18.
Zurück zum Zitat Kumar, S., Singh, K., Chander, S., Goel, E., Singh, P.K., Baral, K.: 2-D analytical drain current model of double-gate heterojunction TFETs with SiO2/HfO2 stacked gate-oxide structure. IEEE Trans. Electron Devices 65, 331–338 (2018)CrossRef Kumar, S., Singh, K., Chander, S., Goel, E., Singh, P.K., Baral, K.: 2-D analytical drain current model of double-gate heterojunction TFETs with SiO2/HfO2 stacked gate-oxide structure. IEEE Trans. Electron Devices 65, 331–338 (2018)CrossRef
19.
Zurück zum Zitat Zhang, L., Lin, X., He, J., Chan, M.: An analytical charge model for double gate tunnel FETs. IEEE Trans. Electron Devices 59, 3217–3223 (2012)CrossRef Zhang, L., Lin, X., He, J., Chan, M.: An analytical charge model for double gate tunnel FETs. IEEE Trans. Electron Devices 59, 3217–3223 (2012)CrossRef
20.
Zurück zum Zitat Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.: Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices 57, 827–834 (2010)CrossRef Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.: Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices 57, 827–834 (2010)CrossRef
21.
Zurück zum Zitat Sze, S.: Physics of Semiconductor Devices. Wiley, New York (1981) Sze, S.: Physics of Semiconductor Devices. Wiley, New York (1981)
22.
Zurück zum Zitat Dash, S., Mishra, G.P.: A new analytical threshold voltage model of cylindrical gate tunnel FET(CG-TFET). Superlattices Microstruct. 86, 211–220 (2015)CrossRef Dash, S., Mishra, G.P.: A new analytical threshold voltage model of cylindrical gate tunnel FET(CG-TFET). Superlattices Microstruct. 86, 211–220 (2015)CrossRef
23.
Zurück zum Zitat Ortiz-Conde, A., Garcia Sanchez, F.J., Liou, J., Cerdeira, A., Estrada, M., Yue, Y.: A review of recent MOSFET threshold voltage extraction methods. Microelectron. Reliab. 42, 583–596 (2002)CrossRef Ortiz-Conde, A., Garcia Sanchez, F.J., Liou, J., Cerdeira, A., Estrada, M., Yue, Y.: A review of recent MOSFET threshold voltage extraction methods. Microelectron. Reliab. 42, 583–596 (2002)CrossRef
24.
Zurück zum Zitat Arafat Mahmud, M., Subrina, S.: Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple material double-gate MOSFET. J. Comput. Electron. 15, 525–536 (2016)CrossRef Arafat Mahmud, M., Subrina, S.: Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple material double-gate MOSFET. J. Comput. Electron. 15, 525–536 (2016)CrossRef
Metadaten
Titel
A novel 2-D analytical model for the electrical characteristics of a gate-all-around heterojunction tunnel field-effect transistor including depletion regions
verfasst von
C. Usha
P. Vimala
T. S. Arun Samuel
M. Karthigai Pandian
Publikationsdatum
25.04.2020
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 3/2020
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-020-01503-8

Weitere Artikel der Ausgabe 3/2020

Journal of Computational Electronics 3/2020 Zur Ausgabe

Neuer Inhalt