A Novel Algorithm for Obstacle Aware RMST Construction during Routing in 3D ICs

Three dimensional integrated circuits offer an attractive alternative to 2D planar ICs by providing increased system integration by either increasing functionality or combining different technologies. Routing phase during layout design of 3D ICs plays a critical role. The problem again becomes worse in presence of obstacles across the routing layers. This obstacle aware routing tree construction has become a challenging problem among the researchers recently. In this work, an efficient algorithm has been proposed for the construction of rectilinear minimum Steiner tree (RMST) in presence of obstacles across the routing layers using a shortest pair approach. Due to ever increasing design complexity issues, careful measures have been taken to reduce the time complexity of the proposed algorithm. The novelties of this work may be stated as follows (i) proposed algorithm helps to construct an RMST in presence of obstacles, (ii) time complexity of the proposed algorithm is very much competitive with available tools, (iii) proposed algorithm efficiently reduces the number of Steiner points during the construction of RMST in presence of obstacles in comparison to the standard solution available in absence of obstacles. Experimental results are quite encouraging.