A novel flip-flop based error free, area efficient and low power pipeline architecture for finite impulse recursive system

An error free, area efficient and low power pipeline architecture for finite impulse recursive signal processing system on chip (SOC) is proposed. The pipeline stage is implemented for the FIR filter which forms the signal conditioning block of the SOC in 60 and 90 nm technology. The design, implementation and testing is performed using Altera Quartus 9.1, cyclone device family for 60 and 90 nm technology. The pipelining is designed with 3 and 5 stages. The combinational block consists of processing elements like array multiplier and ripple carry adder. The registers of the pipelining is designed using normal D flip-flop, Autogated and Razor flip-flop. The pipelining architecture is further extended towards shared component architecture. The proposed shared component architecture reduces the critical path, number of components by which area is reduced and power consumption. The proposed design reduces the error with fewer timing penalty. The results are compared with existing methods and the efficiency of proposed method is improved. The proposed flip flop is compared with the existing flip-flop and found that the static power consumption is reduced by 8% and dynamic power consumption by 56%. The proposed pipelined shared component architecture reduces the power consumption by 10% for static power and 75% for dynamic power. From the machine cycles execution analysis it is found that the proposed design saves clock cycles when an error occurs. When area is considered the proposed architecture contains less number of multipliers.