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2013 | Buch

A Practical Introduction to Hardware/Software Codesign

verfasst von: Patrick R. Schaumont

Verlag: Springer US

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Über dieses Buch

This textbook serves as an introduction to the subject of embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions.

Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which will make the material in this book applicable to a greater number of courses where these tools are already in use. More examples and exercises have been added throughout the book.

“If I were teaching a course on this subject, I would use this as a resource and text. If I were a student who wanted to learn codesign, I would look for a course that at least used a similar approach. If I were an engineer or engineering manager who wanted to learn more about codesign from a very practical perspective, I would read this book first before any other. When I first started learning about codesign as a practitioner, a book like this would have been the perfect introduction.”

--Grant Martin, Tensilica--

Inhaltsverzeichnis

Frontmatter

Basic Concepts

Frontmatter
Chapter 1. The Nature of Hardware and Software
Abstract
Hardware/software codesign is the activity of partitioning an application into a flexible part, mapped into software, and a fixed part, mapped into hardware. The flexible part includes C programs, configuration data, parameter settings, bitstreams, and so forth. The fixed part consists of programmable components such as microprocessors and coprocessors. We’ll first consider several technological and economical reasons for implementing electronic systems in this fashion. Next, we consider the design space of programmable components. A key observation is that there is a trade-off between flexibility and efficiency – with efficiency either in the sense of performance, or else in the sense of energy-consumption. A third part in this chapter will define the abstraction levels of hardware and software for the purpose of this book. And finally, we will also define three terms that play a vital role in this book, namely the terms concurrent, parallel, and sequential.
Patrick R. Schaumont
Chapter 2. Data Flow Modeling and Transformation
Abstract
By nature, hardware is parallel and software is sequential. As a result, software models (C programs) are not very well suited to capture hardware implementations, and vice versa, hardware models (RTL programs) are not a good abstraction to describe software. However, designers frequently encounter situations for which a given design may use either hardware or software as a target. Trying to do both (writing a full C program as well as a full hardware design) is not an option; it requires the designer to work twice as hard. An alternative is to use a high-level model, which enables the designer to express a design without committing to a hardware or a software implementation. Using a high-level model, the designer can gain further insight into the specification, and decide on the right path for implementation.
Patrick R. Schaumont
Chapter 3. Data Flow Implementation in Software and Hardware
Abstract
The data flow model of computation is fully concurrent, and it is not committed to either a sequential or parallel implementation. Therefore, a single specification can be used to target software as well as hardware. This chapter describes the implementation of data flow systems in hardware and software on three different design targets. The first target is a software implementation of the data flow graph. Appropriate software scheduling techniques are needed to implement the data flow schedule. The second target is a fully parallel hardware implementation of the data flow graph. In this implementation, each actor maps into a separate hardware module, and individual modules synchronize through their token communications. The third target is hybrid: a combination of software and a hardware coprocessor. In this case, a data flow graph is partitioned over hardware and software. This chapter demonstrates the flexibility and convenience of a data flow specification under multiple targets.
Patrick R. Schaumont
Chapter 4. Analysis of Control Flow and Data Flow
Abstract
In the previous chapter, we discussed the data flow model of computation. Fundamental to this model is the decomposition of a system into individual nodes (actors), which communicate through unidirectional, point-to-point channels (queues). The resulting system model is represented as a graph. The data flow model of computation describes concurrent computations. We discussed techniques to create a hardware or a software implementation starting from the same data flow model.
Patrick R. Schaumont

The Design Space of Custom Architectures

Frontmatter
Chapter 5. Finite State Machine with Datapath
Abstract
In this chapter, we introduce a fundamental building block of custom hardware design: the Finite State Machine with Datapath (FSMD). An FSMD combines a controller, modeled as a finite state machine (FSM), and a dapapath. The datapath receives commands from the controller and performs operations as a result of executing those commands. The controller uses the results of datapath operations to make decisions and to steer control flow. The FSMD model will be used throughout the remainder of the book as the reference model for the ‘hardware’ part of hardware/software codesign. We will introduce a syntax for FSMD through the GEZEL language. The cosimulation tools used in conjunction with this book rely on the GEZEL language. We will discuss several alternate language mappings for the FSMD model, including VHDL, Verilog and SystemC. Finally, we will also describe a few formal properties of the FSMD model, and we will define a proper FSMD as one which leads to a race-free and deterministic hardware implementation.
Patrick R. Schaumont
Chapter 6. Microprogrammed Architectures
Abstract
This chapter discusses the design of micro-programmed controllers and datapaths. The Finite State Machine controller in an FSMD is non-programmable. By substituting the FSM for a programmable controller, you obtain a micro-programmed architecture. The advantage of a programmable architecture is obviously the flexibility to implement multiple applications on the same architecture.
Patrick R. Schaumont
Chapter 7. General-Purpose Embedded Cores
Abstract
The most successful programmable component on silicon is the micro-processor. Fueled by a well-balanced mix of efficient implementations, flexibility, and tool support, microprocessors have grown into a cornerstone of electronic design. This chapter reviews the major features of microprocessor architectures, and in particular of RISC (Reduced Instruction Set Computer) processors. The topic of microprocessors is a very broad one; entire books are devoted to its discussion. The objectives of this chapter are more modest. Our objective is to build insight into the relation between a C program and its execution on a micro-processor. This insight is crucial for hardware-software codesign. Indeed, the interaction between custom hardware coprocessors and software will always proceed through the microprocessor. The low-level behavior of software on a microprocessor therefore plays a fundamental role in the efficiency of a system that uses hardware as well as software components. The chapter covers four different aspects of C program execution on RISC processors: the architectural and behavioral features of RISC processors, the implementation and low-level organization of C programs, the role and use of compiler tools, and the role and the use of simulation tools. Much more can be said on micro-processors. The Further Reading section at the end of this chapter provides additional suggestions for self-study.
Patrick R. Schaumont
Chapter 8. System on Chip
Abstract
In the previous chapters, we discussed various digital architectures that each present a different trade-off between flexibility and specialization. The trend was from specialized towards more general and more flexible. In this chapter, we complete the discussion with a generic architecture-specialization concept. The concept is called System-on-Chip (SoC). An SoC combines one or more general-purpose processors with dedicated coprocessors and on-chip memory, on a single chip. An SoC architecture provides general-purpose computing capabilities along with a few highly-specialized functions, adapted to a particular design domain. This chapter reviews the cast of players in the system-on-chip concept, and it describes its key characteristics. The chapter also discusses the construction of GEZEL SoC models.
Patrick R. Schaumont

Hardware/Software Interfaces

Frontmatter
Chapter 9. Principles of Hardware/Software Communication
Abstract
A hardware/software communications channel connects two parallel and heterogeneous entities, hardware and software. The design of such a channel introduces several interesting and challenging problems in computer design, and this chapter describes the underlying ideas of the solution. The first of these is synchronization, the structured interaction of parallel and independent entities. A second important discussion in this chapter is performance analysis of hardware/software communication links. This leads to the distinction of computation-constrained systems from communication-constrained systems. The final discussion is the distinction between loosely-coupled and tightly-coupled hardware-software interfaces.
Patrick R. Schaumont
Chapter 10. On-Chip Busses
Abstract
The on-chip bus is the backbone of the SoC, and it is a means to efficiently connect various components including processors, memory, and peripherals. The challenges for an on-chip bus are not minor: it has to accommodate a wide range of communication needs with a single, unified architecture. In this chapter we review the key characteristics of the on-chip bus through the example of ARM/AMBA, IBM/Coreconnect, Altera/Avalone, and Wishbone. We also look at some of the long-term challenges for on-chip interconnect, and their effect on the design of hardware-software interfaces.
Patrick R. Schaumont
Chapter 11. Microprocessor Interfaces
Abstract
In this chapter, we discuss the various techniques available on a microprocessor to implement a hardware/software communication link. We will discuss three different approaches at building these interfaces, each resulting in a different programming model for custom hardware modules. We will cover memory-mapped interfaces, coprocessor interfaces, and custom-instruction interfaces, and we illustrate this with several example implementations.
Patrick R. Schaumont
Chapter 12. Hardware Interfaces
Abstract
This chapter discusses attaching a custom hardware module to a hardware/software interface (such as a memory-mapped interface, a coprocessor interface, or a custom-instruction interface). This requires the design of a hardware interface to encapsulate the custom hardware module and to make it compatible with a given hardware/software interface. There are two orthogonal aspects to hardware interface design. The first, data design, defines how to transfer data from software to custom hardware and back. The second, control design, defines how to implement a software control strategy for the custom hardware. The combination of data design and control design define the programmer’s model, the abstract software view of the hardware module. This chapter will address each of these aspects.
Patrick R. Schaumont

Applications

Frontmatter
Chapter 13. Trivium Crypto-Coprocessor
Abstract
Stream ciphers are complex state machines that generate an infinite stream of pseudo-random bits starting from a single key. These bits can be used as a keystream in encryption and decryption operations. In this chapter we’ll discuss the implementation of such a stream cipher algorithm, called Trivium, as a co-processor. The co-processor is attached to a host processor. The software on that host processor initializes the Trivium coprocessor, and retrieves a very long (infinite) keystream. We consider different types of host processors, including an 8-bit 8051 micro-controller, a 32-bit StrongARM RISC, and a 32-bit Microblaze processor. We will evaluate the impact of different types of hardware-software interfaces on the performance of the overall design. We will also investigate the path to implementation on an FPGA.
Patrick R. Schaumont
Chapter 14. AES Co-processor
Abstract
In this chapter we will study the implementation of the Advanced Encryption Standard as a hardware accelerator – a hardware module that completes the encryption on behalf of software. We’ll create two implementations: a memory-mapped encryption coprocessor for ARM, and a custom-instruction encryption/decryption implementation for Nios. Both of these cases will highlight the impact of hardware interface design on the overall implementation. The chapter includes important sections of the source code, but these are not fully self-contained. The reader can refer to the book website for a complete set of design files.
Patrick R. Schaumont
Chapter 15. CORDIC Co-processor
Abstract
The Coordinate Rotation Digital Computer Algorithm (CORDIC for short) is a well known algorithm to compute rotations using simple, integer arithmetic. The algorithm implements a conversion between rectangular (X, Y ) coordinates and polar (r, θ) coordinates. In this chapter, we discuss the design of a coprocessor that implements the CORDIC algorithm. We will use a Fast-Simplex-Link (FSL) interface. We also discuss a prototype implementation of the design on a Spartan 3E Starter Kit, and show how to resolve the communication bottlenecks originating from inefficient hardware/software interfaces.
Patrick R. Schaumont
Backmatter
Metadaten
Titel
A Practical Introduction to Hardware/Software Codesign
verfasst von
Patrick R. Schaumont
Copyright-Jahr
2013
Verlag
Springer US
Electronic ISBN
978-1-4614-3737-6
Print ISBN
978-1-4614-3736-9
DOI
https://doi.org/10.1007/978-1-4614-3737-6

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