A new architecture for the practical implementation of a quantum computer is presented in this paper. The architecture makes use of the recombination statistics that govern semiconductor devices and I particular quantum phenomena occurring inside the forbidden gap of a semiconductor filled with a controlled amount of impurities. The occupation of a single trap by an electron is used for the representation of the qubit, whereas illuminating techniques are used for the controlled transition of the electrons between gap levels. The way these transitions correspond to the logical equivalent of quantum gates is being demonstrated by the implementation of the quantum Controlled-NOT (CNOT) gate. Measuring techniques of the final computational outcome based on macroscopic properties of a semiconductor are discussed.
The above techniques are then combined for the design of a quantum circuit, which implements the Shor’s factoring algorithm. The physical model for the interconnection of quantum gates scaled to a full quantum computer is given along with the design of the algorithm. Finally, some error estimations are given together with some proposed mechanisms to reduce this error to acceptable levels using known quantum error correction techniques.