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Erschienen in:
2006 | OriginalPaper | Buchkapitel
A Quantum Hydrodynamic Simulation of Strained Nanoscale VLSI Device
verfasst von : Shih-Ching Lo, Shao-Ming Yu
Erschienen in: Computational Science – ICCS 2006
Verlag: Springer Berlin Heidelberg
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Strained silicon field effect transistor (FET) has been known for enhancing carrier mobility. The stained Si channel thickness, the Si
1 − − x
Ge
x
composition fraction and the Si
1 − − x
Ge
x
layer thickness are three crucial parameters for designing strained Si/SiGe MOSFET. Mobility enhancement and device reliability may be unnecessarily conservative. In this paper, numerical investigation of drain current, gate leakage and threshold voltage for strained Si/SiGe MOSFET are simulated under different device profiles. According to our results, the optimal combination of parameters are as follows: stained Si channel thickness is 7 nm, Ge content is 20%, and the Si
1 − − x
Ge
x
layer thickness should be chosen between 20~50 nm.