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2010 | OriginalPaper | Buchkapitel

4. A Reduced-Dimension Processor Model

Incorporating Microarchitectural Parameters and Software’s Dynamic Characteristics

verfasst von: Azam Beg

Erschienen in: Advances in Machine Learning and Data Analysis

Verlag: Springer Netherlands

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Abstract

Architectural simulators used for microprocessor design study and optimization can require large amount of computational time and/or resources. In such cases, models can be a fast alternative to lengthy simulations, and can help reach a designer near-optimal system configuration. However, the non-linear characteristics of a processor system make the modeling task quite challenging. The models not only need to incorporate the micro-architectural parameters but also the dynamic behavior of programs. This paper presents a hybrid (hardware/software), non-linear model for processors. The model provides accurate predictions of processor throughput for a wide range of design space. We used different groups of code basic blocks to investigate their relationships to the execution efficiency of a superscalar processor. For this purpose, we utilized the frequencies of the blocks to represent runtime nature of ten benchmark programs. We were able to reduce the number of hardware and software parameters by employing correlation coefficients and principal component analysis.

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Fußnoten
1
The acronyms NN and FFNN are used alternatively in this work.
 
2
Legends for Table 4.2: CC = correlation coefficient > 0.5; bPred = branch predictor type (nominal); commit = commit unit width (no. of instructions); decoder = decoder unit width (no. of instructions); fetchIFQ = instruction fetch unit size (no. of instructions); brPredLat = fetch latency (no. of cycles); busRatio = ratio of front-end speed to processor speed; issue = issue unit width (no. of instructions); LSQ = load/store queue (no. of instructions); fpALU = no. of floating point ALUs; fpMult = no. of floating point multipliers; iALU = no. of integer ALUs; iMult = no. of integer multipliers; RUU = capacity of register update units (no. of instructions); BB1 = no. of basic blocks containing one instruction; BB1–4 = no. of basic blocks containing one to four instructions, BB5- = no. of basic blocks containing five or more instructions, etc.
 
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Metadaten
Titel
A Reduced-Dimension Processor Model
verfasst von
Azam Beg
Copyright-Jahr
2010
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-90-481-3177-8_4

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