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Über dieses Buch

The purpose of this introductory book is to couple the teaching of chaotic circuit and systems theory with the use of field programmable gate arrays (FPGAs).

As such, it differs from other texts on chaos: first, it puts emphasis on combining theoretical methods, simulation tools and physical realization to help the reader gain an intuitive understanding of the properties of chaotic systems. Second, the "medium" used for physical realization is the FPGA. These devices are massively parallel architectures that can be configured to realize a variety of logic functions. Hence, FPGAs can be configured to emulate systems of differential equations.

Nevertheless maximizing the capabilities of an FPGA requires the user to understand the underlying hardware and also FPGA design software. This is achieved by the third distinctive feature of this book: a lab component in each chapter. Here, readers are asked to experiment with computer simulations and FPGA designs, to further their understanding of concepts covered in the book.

This text is intended for graduate students in science and engineering interested in exploring implementation of nonlinear dynamical (chaotic) systems on FPGAs.



Chapter 1. Introduction

This chapter will provide a historical overview of chaos and FPGAs. We will begin with a history of how chaos was observed (but unidentified) in a problem related to astronomy and made its way into electronics. On the flip side, the history of FPGAs is a part of the history of Silicon Valley. Next we will look at some very important and fundamental concepts: linearity versus nonlinearity, equilibrium points and Jacobi linearization. As you read through the chapter and work through the exercises, you will realize that nonlinear systems have “rich behaviour” compared to linear systems. Yet you will also notice that relatively simple nonlinear systems can give rise to this rich behaviour.

Bharathwaj Muthuswamy, Santo Banerjee

Chapter 2. Designing Hardware for FPGAs

In this chapter we will cover many of the basic concepts behind FPGA design. We start with an overview of our hardware platform, go through a quick introduction to the Quartus toolset and then review combinational along with sequential logic. We will conclude with the all important concept of timing closure. Although we cover a particular hardware platform, the material in this chapter can be adopted to understand other FPGA hardware platforms. This chapter, along with Chap.


, lay the groundwork for the rest of the book. Nevertheless, please understand that majority of this chapter is meant primarily as a review. However, the conceptual material on abstracting the FPGA development flow via Simulink should not be skipped.

Bharathwaj Muthuswamy, Santo Banerjee

Chapter 3. Chaotic ODEs: FPGA Examples

In this chapter, we will focus on realizing chaotic systems on an FPGA. We will first show a simple numerical method for specifying chaotic systems on the FPGA and then realize the Lorenz system. We will then illustrate the complete FPGA design process of functional simulation, in-system debugging and physical implementation. In order to illustrate the robustness of FPGAs, we will conclude this chapter by realizing a chaotic system with a hyperbolic tangent nonlinearity.

Bharathwaj Muthuswamy, Santo Banerjee

Chapter 4. Bifurcations

This chapter will explore a variety of routes that lead to chaos in dynamical systems, through simulation and FPGA experiments. The goal of this chapter is simply for the reader to understand that a system is chaotic for a certain range of parameters and there are interesting mechanisms that lead to the chaotic behavior.

Bharathwaj Muthuswamy, Santo Banerjee

Chapter 5. Chaotic DDEs: FPGA Examples and Synchronization Applications

This chapter explores particular advantage(s) of FPGAs for investigating nonlinear dynamics—realization of time delayed chaotic systems. These advantages are the availability of on-chip memory and the fact that generate statements in VHDL can be used to elegantly implement arbitrary (limited by on-chip memory and the number of FPGA logic elements) length delay chains. We will also explore synchronization applications in chaotic DDEs using the FPGA.

Bharathwaj Muthuswamy, Santo Banerjee


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