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30.06.2022

A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

verfasst von: Ancy Joy, Jinsa Kuruvilla

Erschienen in: Wireless Personal Communications

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Abstract

Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals.
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Metadaten
Titel
A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis
verfasst von
Ancy Joy
Jinsa Kuruvilla
Publikationsdatum
30.06.2022
Verlag
Springer US
Erschienen in
Wireless Personal Communications
Print ISSN: 0929-6212
Elektronische ISSN: 1572-834X
DOI
https://doi.org/10.1007/s11277-022-09865-x