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Erschienen in: Journal of Computational Electronics 3/2017

19.05.2017

A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture

verfasst von: Kunal Sinha, Sanatan Chattopadhyay, Partha Sarathi Gupta, Hafizur Rahaman

Erschienen in: Journal of Computational Electronics | Ausgabe 3/2017

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Abstract

In this work, a germanium (Ge) fin-shaped field-effect transistor (FinFET) with silicon–germanium (SiGe) embedded source/drain architecture has been studied and the role of SiGe stressor material volume on induced channel stress has been investigated thoroughly for different stressor lengths/volumes inside the constant source/drain region. A 15-nm-long stressor from channel source/drain interface into the 50-nm-long source/drain region has been found to induce maximum compressive stress in the channel. This helps to improve the p-channel device performance and complete filling of source/drain region by the same SiGe incorporate tensile channel stress which improves the n-channel device performance. The nature and amount of induced channel stress have been found to depend on the relative volume of the channel, source/drain and SiGe stressor regions. A significant improvement is observed in the transconductance of the device over the drain current \(({g}_{\mathrm {m}}/{I}_{\mathrm {d}})\) ratio for higher channel stress, indicating better performance of amplifier using uni-axially strained channel Ge FinFET.

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Metadaten
Titel
A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture
verfasst von
Kunal Sinha
Sanatan Chattopadhyay
Partha Sarathi Gupta
Hafizur Rahaman
Publikationsdatum
19.05.2017
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 3/2017
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-017-1003-x

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