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Journal of Computational Electronics

26.08.2016

A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET

verfasst von: Vadthiya Narendar, Saurabh Rai, Siddharth Tiwari

Erschienen in: Journal of Computational Electronics

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Abstract

Double-gate (DG) MOSFETs are regarded as leading front runners in the semiconductor industry. To alleviate the short-channel effects (SCEs) in DG MOSFET, a new underlap dual-material (DM) DG FinFET device structure is proposed, which has the advantages of an underlapped device as well as of a dual-material gate device (DMG). A 2D analytical surface potential and subthreshold current modelling of the proposed device has been done by solving the Poisson’s equation. It has also been found that the results obtained analytically are in good agreement with numerical simulation results. As the underlap length \((L_\mathrm{un})\) increases, a substantial reduction of subthreshold current due to enhanced gate control over channel regime is observed. The DMG used in the structure improves average velocity of the carriers which leads to superior drive current of the device. The proposed device structure has been compared with underlap single-metal (SM) DG FinFET structures in terms of electrical characteristics, such as drain-induced barrier lowering (DIBL). The comparison confirms the suppression of SCEs with increasing \(L_\mathrm{un}\) in both the structures, but it is more significant in the case of underlap DMDG FinFET structures.

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Literatur
1.
Moore, G.: Cramming more components onto integrated circuit. Proc. IEEE 86(1), 82–85 (1998)CrossRef
2.
Robert, H.D., Fritz, H.G., Hwa-Nien, Y., V Leo, R., Ernest, B., Ander, R.L.: Designof ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid State Circuits 9, 256–268 (1974)CrossRef
3.
4.
Chenming, H.: Modern Semiconductor Devices for Integrated Circuits. Prentice Hall, Upper Saddle River (2009)
5.
Surya, V., Jerry, G.F.: Short-channel effects in SOI MOSFET’s. IEEE Trans. Electron Dev. 36(3), 522–528 (1989)CrossRef
6.
David, J.F., Yuan, Tr, Hon-Sum, P.W.: Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Dev. Lett. 19(10), 385–388 (1998)CrossRef
7.
Hon-Sum, P.W.: Beyond the conventional transistor. IBM J. Res. Dev. 46(2), 133–168 (2002)
8.
Tripathi, S., Narendar, V.: A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET. Superlattices Microstruct. 83, 476–487 (2015)CrossRef
9.
Clement, H.W., et al.: A comparative study of advanced MOSFET concepts. IEEE Trans. Electron Dev. 43(10), 1742–1753 (1996)CrossRef
10.
Yan, Ran-Hong, Abbas, O., Kwing, F.L.: Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Dev. 39, 1704–1710 (1992)CrossRef
11.
Yang, P.C., Li, S.S.: Analysis of current-voltage characteristics of fully depleted SOI MOSFETs. Solid State Electron. 36, 685–692 (1993)CrossRef
12.
Vadthiya, N., Ram, A.M.: Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs). Superlattices Microstruct. 85, 357–369 (2015)CrossRef
13.
Colinge, J.P.: Multiple-gate SOI MOSFETs. Solid State Electron. 48, 897–905 (2004)CrossRef
14.
Colinge, J.P.: Multi-gate SOI MOSFETs. Microelectron. Eng. 84(6), 2071–2076 (2007)CrossRef
15.
Park, J.T., Colinge, J.P., Diaz, C.H.: Pi-Gate SOI MOSFET. IEEE Electron Device Lett. 22(8), 405–406 (2001)CrossRef
16.
Park, J.T., Colinge, J.P.: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Electron Device Lett. 49(12), 2222–2229 (2002)CrossRef
17.
Raskin, J.P., Viviani, A., Flandre, D., Colinge, J.P.: Substrate crosstalk reduction using SOI technology. IEEE Electron Device Lett. 44(12), 2252–2261 (1997)CrossRef
18.
Konard Young, K.: Short-channel effect in fully depleted SOI MOSFET’s. IEEE Electron Device Lett. 36(2), 399–402 (1989)CrossRef
19.
Yuan, T., et al.: An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Devices Lett. 21(5), 245–247 (2000)CrossRef
20.
Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Chenming, H.: FinFET - A self-aligned double-gate MOSFET scalable beyond 20nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)CrossRef
21.
Qiang, C.: A physical short-channel threshold voltage model for undoped Symmetric Double-Gate MOSFETs. IEEE Trans. Electron Devices 50(7), 1631–1637 (2003)CrossRef
22.
Suzuki, K., Tanaka, T., Tasaka, Y., Horie, H., Arimoto, Y.: Scaling theory for double-gate SOI MOSFETs. IEEE Trans. Electron Devices 40(12), 2326–2329 (1993)CrossRef
23.
Suzuki, K., Sugii, T.: Analytical models for n\(^{+}\)-p\(^{+}\) double-gate SOI MOSFETs. IEEE Trans. Electron Devices 42(11), 1940–1948 (1995)CrossRef
24.
Sang-Hyun, Oh, Monroe, D., Hergenrother, J.M.: Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Trans. Electron Devices 21(9), 445–447 (2000)CrossRef
25.
Liang, X., Taur, Y.: A 2-D Analytical Solution for SCEs in DG MOSFETs. IEEE Trans. Electron Devices 51(8), 1385–1391 (2004)CrossRef
26.
Boeuf, F., Skotnicki, T., et al.: 16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimization. IEDM Tech. Dig., pp. 637–640 (2001)
27.
Bansal, A., Paul, B.C., Roy K.: Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices. In: Proc. IEEE SOI Conf., pp. 94–95 (2004)
28.
Hyunjin, L., Jongho, L., Hyungcheol, S.: DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure. IEEE Trans. Nanotechnol. 1(4), 219–225 (2002)CrossRef
29.
Bansal, A., Paul, B.C., Roy, K.: Modeling and optimization of fringe capacitance of nanoscale DGMOS devices. IEEE Trans. Electron Devices 52(2), 256–262 (2005)CrossRef
30.
Bansal, A., Roy, K.: Analytical subthreshold potential distribution model for gate underlap double-gate MOS transistors. IEEE Trans. Electron Devices 54(7), 1793–1798 (2007)CrossRef
31.
Zhou, X., Long, W.: A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology. IEEE Trans. Electron Devices 45(12), 2546–2548 (1998)CrossRef
32.
Long, W., Ou, H., Kuo, J.-M., Chin, K.K.: Dual-material gate (DMG) field effect transistor. IEEE Trans. Electron Devices 46(5), 865–870 (1999)CrossRef
33.
Zhou, X.: Exploring the novel characteristics of hetro-material gate field-effect transistors (HMGFET’s) with gate-material engineering. IEEE Trans. Electron Devices 47(1), 113–120 (2000)CrossRef
34.
Reddy, G.V., Kumar, M.J.: A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Trans. Nanotechnol. 2(2), 260–268 (2005)CrossRef
35.
Polishchuk, I., Ranade, P., King, T.-J., Chenming, H.: Dual work function metal gate CMOS technology using metal interdiffusion. IEEE Electron Device Lett. 22(9), 444–446 (2001)CrossRef
36.
Guillaumot B.: 75 nm damascene metal gate and high-k integration for advanced CMOS devices. IEDM. pp. 355–358 (2002)
37.
Liu, J., Wen, H.C., Lu, J.P., Kwong, D.L.: Dual-work-function metal gates by full silicidation of Poly-Si with Co-Nibi-layers. IEEE Electron Device Lett. 26(4), 228–230 (2005)CrossRef
38.
Zhang, Z., Song, S.C., et al.: Integration of dual metal gate CMOS on high-k dielectrics utilizing a metal wet etch process. Electrochem. Solid State Lett. 8, G271–G274 (2005)CrossRef
39.
Ren, C., Yu, H.Y., et al.: A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate. IEEE Electron Device Lett. 25(8), 580–582 (2004)CrossRef
40.
Efavi, J.K., Mollenhauer, T., Wahlbrink, T., Gottlob, H.D.B., Lemme, M.C., Kurz, H.: Tungsten workfunction engineering for dual metal gate nano-CMOS. J. Mater. Sci. Mater. Electron. 16, 433–436 (2005)CrossRef
41.
Device Simulation Software: Silvaco International. Santa Clara, CA (2012)
42.
Chen, Q., Harrell, E.M., Meindl, J.D.: A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs. IEEE Trans. Electron Devices 50(7), 1631–1637 (2003)CrossRef
43.
Zahn, M.: Electromagnetic Field Theory: A Problem Solving Approach. Wiley, New York (1979)
44.
Aritra, D., Chakravorty, A., DasGupta, N., DasGupta, A.: Analytical model of subthreshold current and slope for asymmetric 4-T and 3-T double-gate MOSFETs. IEEE Trans. Electron Devices 55(12), 3442–3449 (2008)CrossRef
45.
Havaldar, D.S., Katti, G., DasGupta, N., DasGupta, A.: Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson’s equation. IEEE Trans. Electron Devices 53(4), 737–742 (2006)CrossRef
46.
Yeh, P.C., Fossum, J.G.: Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology. IEEE Trans. Electron Devices 42(9), 1605–1613 (1995)CrossRef
Metadaten
Titel
A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET
verfasst von
Vadthiya Narendar
Saurabh Rai
Siddharth Tiwari
Publikationsdatum
26.08.2016
Verlag
Springer US
Erschienen in
Journal of Computational Electronics
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0890-6