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Über dieses Buch

Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts.
A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation.
A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers.
A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model.
A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits.
The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.

Inhaltsverzeichnis

Frontmatter

1. Introduction

Abstract
Continuing advances in design techniques and fabrication process technology are resulting in the design and manufacture of very high speed digital systems. Digital system operation at high clock speeds does not allow for much design margin, so these circuits have to be designed under very tight timing constraints. In such a scenario, it is imperative to verify the temporal behavior of such circuit designs before they are sent for fabrication. It is also equally important to test each fabricated chip to ensure that the circuit indeed performs correctly at the specified clock speed.
Mukund Sivaraman, Andrzej J. Strojwas

2. Background

Abstract
Modern-day circuits are characterized by large complexity, numerous false paths for certain classes of circuit designs (e.g., adders which employ speedup techniques, multipliers etc.), very small critical path slacks (due to circuit operation under tight timing constraints), and large variations in component delays (as a result of fluctuations in fabrication processes affecting devices and interconnect with very small feature sizes). Variations in component delays may be correlated to a certain extent due to global fabrication process fluctuations and similar fabrication process effects on neighboring devices. Moreover, decreasing minimum feature sizes, increasing design complexity, and faster circuit operation are resulting in the following: gate outputs seeing significant resistive effects of the interconnect load, the need for long interconnect to be modeled as distributed RC elements, and significant capacitive coupling effects across neighboring signal lines. This is leading to interconnect delays being a significant part of the chip delay, and in many cases even dominating the delay through the switching elements.
Mukund Sivaraman, Andrzej J. Strojwas

3. Primitive Path Delay Fault Identification

Abstract
Under a path delay fault model, one way to guarantee correct timing behavior of the circuit would be to test all paths individually with tests which remain valid regardless of delay faults on other paths (i.e., RV-tests). Unfortunately, finding tests for all paths is impossible in circuits which have non-RV-testable paths. Hence, research in this context has been directed towards finding a subset of paths such that if these paths are guaranteed not to have delay faults, it can be inferred that the circuit will exhibit correct temporal behavior for all input vectors regardless of delay faults on the rest of the paths. Various classifications of paths based on delay fault testability have been proposed in the literature (Figure 15).
Mukund Sivaraman, Andrzej J. Strojwas

4. Timing Analysis

Abstract
From Theorem 1 in Section 2.2 and from the argument in Section 3.1, it can be inferred that the primitive PDFs bound the time at which the circuit output stabilizes to its final logic value. In other words, the maximum of the primitive PDF delays is a valid bound for the maximum circuit delay. We elaborate on this in Section 4.1, and prove that this in fact is exactly equal to the maximum circuit delay under the floating mode of operation. We then describe in Section 4.2 how our primitive PDF identification procedure from the previous chapter can be extended to compute this delay [108]. We discuss the advantages, limitations, and applicability of the Primitive PDF Identification based Timing Analysis (PITA) strategy in Section 4.3 and Section 4.4. Results for benchmark circuits are presented in Section 4.5.
Mukund Sivaraman, Andrzej J. Strojwas

5. Delay Fault Diagnosis

Abstract
Testing fabricated chips for correct temporal behavior is typically done by applying a set of input vector pairs at-speed to the chip under test, and comparing the sampled circuit outputs with their expected logic values. Assuming that the chip is functionally correct, i.e., it produces the correct output values given sufficient time, any discrepancy is the result of one or more delay faults in the fabricated chip. Literature in this context has primarily focused on finding minimal delay test sets with maximal coverage [67][68][69][70][71], i.e., finding a small number of tests which will detect as many delay faults in the circuit as possible. By generating tests which can detect many delay faults in a circuit, the ability to determine which delay fault caused the chip failure gets diminished. Diagnostic testing [87] [88] deals with enhancing the diagnostic ability of tests, i.e., finding test sets which can not only detect delay faults but also distinguish between them.
Mukund Sivaraman, Andrzej J. Strojwas

6. Delay Fault Coverage

Abstract
It is not feasible to test a circuit for delay faults by applying all possible delay tests (i.e., all possible input sequences). For the purposes of delay testing, it is therefore judicious to select a manageable set of test patterns which test each fabricated chip for the presence of delay faults. If a fabricated chip passes a set of delay tests, the confidence one has in the absence of delay faults in the chip is a measure of the effectiveness of the test set. This notion has typically been quantified in terms of the percentage of all possible delay faults which can be detected by the test set. This quantification has been used as a measure of the delay fault coverage of the test set, and has evolved from the definition of fault coverage for functional failures (e.g., stuck-fault coverage), where the coverage of a test set is defined as the percentage of the total number of faults detectable by the test set. However, this quantification is not a realistic metric for delay fault coverage. This is because the size of a delay fault also determines whether or not a delay failure is observed at a circuit output.
Mukund Sivaraman, Andrzej J. Strojwas

7. Epilogue

Abstract
Timing verification and delay fault testing seek to solve seemingly different problems, yet are intimately related areas of research as they are based on similar concepts. This book brings the two areas even closer by relating the circuit stabilization time to sets of paths that are necessary and sufficient to be tested. More precisely, we show that under a test vector pair, the singly/jointly statically sensitized path sets bound the stabilization time of the circuit outputs. This leads to an efficient procedure, called iterative-SSTA, for identifying minimal singly/jointly statically sensitizable path sets (i.e., primitive path sets) which correspond to primitive PDFs.
Mukund Sivaraman, Andrzej J. Strojwas

Backmatter

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