A Unipolar Phase Disposition PWM Technique for Reduced Switch Count Symmetrical Nine-Level Multilevel DC Link Inverter Topology

This paper presents the implementation of single-phase symmetric nine-level Multilevel DC link (MLDCL) inverter topology with Unipolar Phase Disposition (UPD) PWM control scheme. This topology consists of four half-bridge cells which are connected in cascaded manner with eight unidirectional switches in level generator side and to decide the polarity, one full H-bridge with four unidirectional switches have been integrated at the polarity generator side. This topology possesses less per unit standing voltage and high modularity as compared with traditional multilevel inverters like diode clamped flying capacitor and cascaded H-bridge topologies. In order to generate K level output, Phase Disposition (PD) control scheme requires (K-1) high-frequency carriers. However, the proposed UPD control scheme reduces the number of carrier count by half to generate the K level output. The reduction of carrier count reduces control complexity and burden on the processor. The proposed control technique is well suitable for generalized structure of MLDCL topology to any level count. The simulation results of the topology with proposed control technique have been validated through MATLAB/Simulink environment.