A compressor is an applicable part that is broadly operated in VLSI circuits and its systems that take part in an important role in high-speed systems. This article computes that the new 7:3 compressor uses a 7-bit stacking approach using NOR gates that reduces power and delay as well as transistor count when compared to the existing one. In the existing part, the 7:3 compressor was designed in three methods, which are the mirror circuit using XOR, the 4 T using XOR, and the transmission gate using XOR. Among these, the transmission gate using XOR gives the best result. In the recommended work, the stacking approach is used to execute the 7:3 compressor. In the first stage, a two 3-bit stacker approach was used. From the first stage, output is taken for computing output equations S0, C1, and C2. Using the NOR gate in the proposed equations gives a better result. The proposed 7:3 compressor is implemented in an 8*8 Wallace tree multiplier, which implies it will reduce the intermediate parts and consume less power. At 250 nm technology, the proposed design is designed and analysed in a Tanner EDA tool. While analysing its parameters, the percentage reduction in power, delay, and PDP between the existing and proposed 7:3 compressor was 12.82%, 2.87%, and 15.35%, respectively, and the percentage reduction in power, delay, and PDP between the existing and proposed Wallace tree multiplier was 4.2%, 3.01%, and 7.11%., the proposed design gives the greatest performance in the specifications, namely power, delay, and PDP, along with the number of transistor utilization.