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This chapter presents the novel adaptive low-power reconfigurable processor architecture with a run-time adaptive energy management scheme. It exploits the novel concept of Selective Instruction Set Muting with multiple muting modes. The first section analyzes different scenarios, while motivating the need for run-time energy management. Afterwards, the adaptive energy management scheme with the novel concept of Custom Instruction (CI) Set Muting is discussed in Sect. 5.2. In this section different CI muting modes are explained along with the corresponding configuration of sleep transistors for different parts of the reconfigurable fabric. Afterwards, the required power-shutdown infrastructure is discussed. In Sect. 5.2.3 an overview of the energy management scheme is provided highlighting different requirements and steps considered at design-, compile-, and run-time.
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In Xilinx FPGAs, 38% of the leakage power is consumed by the configuration SRAMs [TL03].
At 150 nm, shutting down the currently unused portions of the reconfigurable fabric may not lead to noticeable savings and thus E FPGA_reconf may dominate whereas in case of 65 nm it may be vice versa.
The reactivation energy for one DPC is 3.5 pWs [Te06] while the energy of a hot spot is typically in multiples of mWs, i.e., approximately 10 9 times bigger (see Sect. 5.3.3). Therefore, the DPC reactivation energy overhead is not included in Eq. 5.5, as it does not affect the selection decision at the abstraction level of computational hot spots.
Experiments demonstrate that, in most of the cases, the CI Implementation Version with the fastest execution latency is also the one that provides the minimum dynamic energy due to its speedup, especially in case of tighter performance constraints. However, in terms of reconfiguration energy it might not always be the best choice.
Due to the irreversible nature of the operator \( \cup \) (used in line 21), they cannot be incrementally updated like E HS_CI_DynMin .
The length of a hot spot is predicted from the latency values of different CIs used in the hot spot and their corresponding expected execution frequencies (as predicted by the online-monitoring Sect. 2.3.5).
Instead of idle hardware state monitoring, idle periods of CI usages (i.e., temporarily unused subset of CIs) are exploited for the purpose of energy savings.
As mentioned in Sect. 5.2.2, in order to set a particular muting mode for a CI, the control signals (as specified in Table 5.1) for the sleep transistors (for Logic and the Configuration SRAM) are issued to all DPCs of this CI.
- Adaptive Low-power Reconfigurable Processor Architecture
- Springer New York
- Chapter 5