5. Advanced Approaches for NoC Reuse

The test scheduling approaches discussed in Chap. 4 demonstrated that NoCs can be as a cost-effective TAM as a dedicated bus-based mechanism. Those approaches are based, however, on a single NoC model and on a few assumptions about the NoC, wrappers, and cores. Indeed, guaranteed services (GS) NoCs were assumed to meet the timing constraints of an external tester. Also, all pins at the core interface (functional and test pins) were assumed to be used during test to receive/deliver test data and the core test frequency was assumed to be equal to the NoC operation frequency. Finally, in those first reuse approaches, the available channel bitwidth may be sub-utilized for cores with a small test interface. In this chapter those assumptions are revised and more recent approaches that consider the NoC reuse in more detail are discussed. First, we present alternative test scheduling algorithms and wrapper models that improve channel utilization and consider additional system requirements such as the thermal budget. Then, the characteristics of the NoC communication protocol are taken into account to generate test interfaces for the external tester and test wrappers for the embedded cores. Those wrappers isolate the communication details and aim at using the available NoC bandwidth with no further assumptions. Based on these DfT structures, a test scheduling algorithm for BE NoCs with different topologies is presented.