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Über dieses Buch

From basic architecture, interconnection, and parallelization to power optimization, this book provides a comprehensive description of emerging multicore systems-on-chip (MCSoCs) hardware and software design. Highlighting both fundamentals and advanced software and hardware design, it can serve as a primary textbook for advanced courses in MCSoCs design and embedded systems.

The first three chapters introduce MCSoCs architectures, present design challenges and conventional design methods, and describe in detail the main building blocks of MCSoCs. Chapters 4, 5, and 6 discuss fundamental and advanced on-chip interconnection network technologies for multi and many core SoCs, enabling readers to understand the microarchitectures for on-chip routers and network interfaces that are essential in the context of latency, area, and power constraints.

With the rise of multicore and many-core systems, concurrency is becoming a major issue in the daily life of a programmer. Thus, compiler and software development tools are critical in helping programmers create high-performance software. Programmers should make sure that their parallelized program codes will not cause race condition, memory-access deadlocks, or other faults that may crash their entire systems. As such, Chapter 7 describes a novel parallelizing compiler design for high-performance computing. Chapter 8 provides a detailed investigation of power reduction techniques for MCSoCs at component and network levels. It discusses energy conservation in general hardware design, and also in embedded multicore system components, such as CPUs, disks, displays and memories. Lastly, Chapter 9 presents a real embedded MCSoCs system design targeted for health monitoring in the elderly.



Chapter 1. Introduction to Multicore Systems On-Chip

Systems On-Chip (SoCs) designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. This chapter presents a general introduction to the multicore System-On-Chip (MCSoCs). We start this chapter by describing the needs for multicore systems by today’s general and embedded application domains. Design challenges and basics multicore SoCs hardware and software design are also described.
Abderazek Ben Abdallah

Chapter 2. Multicore SoCs Design Methods

The strong demand for low-power and high-performance multicore systems on chip (MCSoCs) requires quick turn around design methodology. Thus, there is a clear need for efficient methodology for the design of these systems on platforms implementing both hardware and software modules. This chapter describes conventional multicore SoC design methods in details. It also describes a so-called scalable core-based methodology for systematic design environment of application-specific heterogeneous multicore SoC architectures. Although the methodology presented here is general and not limited to special architecture, we will consider a real synthesizable core as a case study to make the discussion easy.
Abderazek Ben Abdallah

Chapter 3. Multicore SoC Organization

Increasing processing power demand for new embedded consumer applications such as mobile multimedia devices, cell phones, and high definition televisions made convectional single-core SoC-based designs no longer suitable to satisfy high performance and low power consumption demands. Moreover, continuous advancements in semiconductor technology enable us to design more complex multicore systems-on-chip (MCSoCs) composed of tens or even hundreds of IP cores. General purpose CPUs, ASICs, DSPs, memory blocks, and I/O and networking devices on a single MCSoC chip are now possible and necessary for current and future complex applications. Understanding the software and hardware building blocks and the computation power of individual components in these complex MCSoCs are necessary for designing power, performance, and cost-efficient systems. This chapter describes in details the architectures and functions of the main building blocks that are used to build such complex MCSoCs.
Abderazek Ben Abdallah

Chapter 4. Multicore SoC On-Chip Interconnection Networks

Global interconnects are becoming the principal performance bottleneck for high-performance multicore SoCs. Since one of the main purposes of SoC design is to shrink the size of the chip as smaller as possible while seeking at the same time for more scalability , higher bandwidth and lower latency. Conventional bus-based systems are no longer reliable architecture for SoC due to a lack of scalability and parallelism integration. During this last decade, network-on-chip (NoC) has been proposed as a promising solution for future systems on chip design. It offers more scalability than the shared bus-based interconnection, and allows more processors/cores to operate concurrently. This chapter presents architecture and design of a two-dimensional NoC system suitable for medium scale multicore SoCs.
Abderazek Ben Abdallah

Chapter 5. Advanced Multicore SoC Interconnects

Next-generation multicore SoC architectures are expected to combine hundreds of tiny cores integrated together to satisfy the power and performance requirements of large complex applications. As the number of cores continues to increase, the employment of low-power and high-throughput on-chip interconnect fabrics become imperative. This chapter describes the architecture and design of two emerging multicore SoC interconnects to overcome the limitations of the conventional (two-dimensional) multicore SoC on-chip interconnect. First, we present the architecture and design of three-dimensional interconnect, which promises a good opportunity for chip architects by porting the 2D-NoC to the third dimension. Second, we describe a mesh-based phototonic on-chip interconnect based on an energy-efficient non-blocking optical switch and contention-aware routing mechanisms.
Abderazek Ben Abdallah

Chapter 6. 3D Integration Technology for Multicore Systems On-Chip

3D integration fully explains the latest microelectronics techniques for increasing chip density and maximizing performance while reducing power consumption. Three-dimensional NoCs/SoCs systems have been showing their advantages against conventional two-dimensional SoCs. Thanks to their reduced average interconnect length and lower interconnect-power consumption inherited from three-dimensional ICs. To ensure their correct functionality, such systems must be fault-tolerant to any short-term malfunction or permanent physical damage to ensure message delivery on time while minimizing the performance degradation as much as possible. This chapter introduces 3D integration technology for fault-tolerant multicore Systems On-Chip .
Abderazek Ben Abdallah

Chapter 7. Parallelizing Compiler for Single and Multicore Computing

To overcome challenges from high power densities and thermal hot spots in microprocessors, multicore computing platforms have emerged as the ubiquitous computing platform from servers to embedded systems . But, providing multiple cores does not directly translate into increased performance for most applications. The burden is placed on software developers to find and exploit coarse-grain parallelism to effectively make use of the abundance of computing resources provided by the systems. With the rise of multicore systems and many-core processors, concurrency becomes a major issue in the daily life of a programmer. Thus, compiler and software development tools will be critical to help programmers create high-performance software. This chapter covers software issues of a so-called parallelizing queue compiler targeted for future single- and multicore embedded systems.
Abderazek Ben Abdallah

Chapter 8. Power Optimization Techniques for Multicore SoCs

Power dissipation continues to be a primary design constraint in single and multicore systems. Increasing power consumption not only results in increasing energy costs, but also results in high die temperatures that affect chip reliability, performance, and packaging cost. Energy conservation has been largely considered in the hardware design in general and also in embedded multicore systems’ components, such as CPUs, disks, displays, memories, and so on. Significant additional power savings can be also achieved by incorporating low-power methods into the design of network protocols used for data communication (audio, video, etc.). This chapter investigates in details power reduction techniques at components and the network protocol levels.
Abderazek Ben Abdallah

Chapter 9. Real Deign of Embedded Multicore SoC for Health Monitoring

Recent technological advances in wireless networking, embedded microelectronics and the Internet allow computer and biomedical scientists to fundamentally modernize and change the way health care services are deployed. Thus, changes and new services are urgently needed to help cope with the imminent crisis in the health care systems caused by current demographic, social, and economic trends in many countries. Electrocardiography (ECG) is an interpretation of the electrical activity of the heart over time captured and externally recorded by electrodes. An effective approach to speed up this and other biomedical operations is to integrate a very high number of processing elements in a single chip so that the massive scale of fine-grain parallelism inherent in several biomedical applications can be exploited efficiently. In this chapter, we present a case study of a real hardware and software design of a multicore SoC architecture targeted for elderly health monitoring .
Abderazek Ben Abdallah


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