Advances in Analogue and Mixed-Signal Integrated Circuits for Space Applications

Inhaltsverzeichnis

1. Frontmatter

2. Data Converters

   1. Frontmatter

   2. Design and Test of a Radiation-Hardened 14-Bit 80 MS/s SAR-Assisted Pipeline-ADC in 28-nm Bulk-CMOS

      Hugo Serra, Fábio Passos, Edgar Albuquerque, Nuno Paulino, Luís Bica Oliveira, João Pedro Oliveira, Paulo Santos, Juan José Medina Del Barrio, Luis Carranza Gonzáles, Mari Ángeles Jalón Victori, Szymon Bednarski, João Goes

      Abstract

      This paper presents the design, implementation, and experimental validation of a 14-bit 80 MS/s calibration-free radiation-hardened pipeline analog-to-digital converter (ADC) realized in 28-nm bulk-CMOS technology. The escalating demand for high-performance ADCs in radiation-rich environments requires robust designs capable of withstanding ionizing radiation-induced errors without compromising performance. Traditional radiation-hardened ADC solutions often entail complex calibration procedures, leading to increased power dissipation and design complexity. In contrast, our proposed ADC architecture leverages the inherent advantages of the pipeline topology, coupled with innovative circuit techniques, to achieve resilience to radiation-induced errors without the need for calibration. By eliminating calibration overhead, the proposed design minimizes energy consumption while maintaining high precision and throughput. The paper outlines the architectural principles, circuit implementations, and the radiation-hardening techniques employed in the ADC design. The performance of the ADC was experimentally characterized for normal operation and for a total-ionizing dose (TID) of 100 krad(Si). The circuit was also tested for single-event effects (SEE), covering single event upset (SEU), single-event latch-up (SEL) and single-event transient (SET) under heavy ions radiation. This calibration-free pipeline ADC represents a significant advancement in radiation-hardened ADC design, offering a compelling solution for applications in space missions, nuclear facilities, and other radiation-prone environments where reliability and energy efficiency are paramount.

   3. A High-Performance TID- and SEE-Tolerant ADC in 65 nm for Space Applications

      Zheyi Li, Laurent Berti, Qiuyang Lin, Jinghao Zhao, Maxim Gorbunov, Geert Thys, Paul Leroux

      Abstract

      In medical, aerospace, and high-energy physics applications, radiation tolerance in ADCs is crucial to guarantee the signal chain’s robustness. This paper presents a 13-bit pipelined-SAR ADC, which is designed by revealing and balancing the tradeoffs between power efficiency and radiation tolerance, achieving 80MS/s and 70.79-dB SNDR with high conversion efficiency and radiation tolerance.

   4. Low Power Radiation Hardened by Design TDC with 8 ps Single-Shot Precision

      Bjorn Van Bockel, Sherif Ali, Ninad Jadhav, Diederik Hendrickx, Ying Cao, Hagen Marien

      Abstract

      A radiation-hardened-by-design time-to-digital converter is presented, featuring a single-shot precision of 8 ps and a zero-dead-zone measurement range of 0 ps up to 3 s. The analog and digital building blocks, along with the overall chip architecture, are developed with a focus on radiation tolerance, enabling robust operation in time-of-flight and time-tagging applications in space.

3. Phase Locked Loops

   1. Frontmatter

   2. Jitter Measurement Results of DARE22G Phase-Locked Loop

      SinNyoung Kim, Ian Thomson, Ilker Eryilmaz, Laurent Berti

      Abstract

      This paper presents the design and characterization of the DARE22G Phase-Locked Loop (PLL) for space applications, targeting low period jitter and radiation hardness. Implemented in 22 nm FD-SOI technology with a ring oscillator-based VCO, the PLL achieves sub-1ps normalized period jitter and wide output frequency range (1.953 MHz to 3 GHz). Measurement results across 30 configurations confirm the PLL’s intrinsic jitter stability, with supply noise effects mitigated through normalization. The DARE22G PLL demonstrates suitability for digital systems requiring robust and precise clock generation.

   3. ITAR-Free Multi-output Low Phase Noise Radiation Hardened by Design PLL

      Maarten Strackx, Bjorn Van Bockel, Peishuo Li, Ugur Yegin, Bert Boons, Karim Talib, Stijn Cuypers, Jasper Gielis, Ying Cao, Hagen Marien

      Abstract

      A fully integrated radiation-hardened all-digital frequency synthesizer, designed in a commercial CMOS technology, is presented in this paper. Radiation hardness by design is implemented in all analog and digital blocks and throughout the chip architecture. The measured normalized phase noise is at −223 dBc/Hz, hence outperforming its measured prototype of −210 dBc/Hz. The synthesizer can work with an on-chip crystal oscillator and supports external references between 10–100 MHz. The chip supports 4 differential outputs at various signaling standards up to 1 GHz and 2 differential RF drivers up to 5 GHz. The radiation tolerance was validated on a prototype, up to a total-ionizing-dose (TID) level of 100 krad (Si) and a single-event latch-up (SEL)/single-event upset (SEU) level of 62.5 meV·cm²/mg.

4. Power Circuits

   1. Frontmatter

   2. A Rad-Hard Quad Power Switch with Fuse-Like Fault Shedding Characteristic

      Sorin Spanoche

      Abstract

      This paper presents a new rad-hard quad power switch with fuse-like load shedding characteristics, offering shorter load shedding times for higher currents and slower times near the load rating current. This i2t characteristic corresponds to a fixed amount of dissipated energy, which is ideal for protecting the switch element. We explain its implementation in silicon and management of switch protection. Test results for regular and radiation environments are provided, along with application examples such as a fault-tolerant redundant switch.

   3. A Scalable COntroller for Power Sources (SCOPS)

      Marc Cousineau, Alan Mathewson, Gregory Almeida, Dimitrios Baramilis, v.d Marcel Burgwal, Matilde Del Pozo, Frederic Pecourt, Emilien Feulliet, Marta Urizar, Philippe Ayzac

      Abstract

      The PROMISE Design Standard and Library is currently being used (and expanded) to develop a very high efficiency, low voltage, high current DC-DC power converter, based on a novel architecture of control, which allows it to be flexible and reconfigurable as a function of application and fault tolerance requirements. This Scalable power source controller IC (SCOPS) is targeted for use in space and satellite applications which require a robust power supply that can deliver the consistent low voltage and high current that is required to drive advanced electronic technologies, all of which are tending towards low voltage operation but which also exhibit very high currents as a function of the numbers of transistors being deployed.

   4. LLC with Flyback DC-DC Converter for the Supply of Low Voltage and High Current in Space Applications

      P. Dubus, K. Makris, A. Mathewson, N. Van Der Blij, J. Oliver, J. Ponin, T. Grzegory, P. Maynadier, C. Papadas

      Abstract

      After a systematic review of topologies for the creation of a low voltage-high current DC-DC converters, an architecture was identified as having potential for addressing the growing power requirements of advanced electronic circuits and systems for use in space applications. The LLC with flyback converter was chosen because it provides compact and low mass potential with high performance against the system specification requirements. This choice was made after extensive numerical simulations of the structure, layout and system level performance.

      A working prototype of this system has now been fabricated and while there is still work to do, there are very encouraging results from the preliminary analysis. These results are presented in this paper with an explanation of the next steps to be adopted.

5. Radiation Testing

   1. Frontmatter

   2. Test System for the Experimental Evaluation of a Low-Power High Performance Four-Channel ADC for Space Applications

      Luis Carranza González, Mari Ángeles Jalón Victori, Juan José Medina Del Barrio

      Abstract

      This paper presents the test system developed to evaluate the static and dynamic parameters of a prototype four-channel, high performance, low power, analog-to-digital converter (QUAD-ADC) exposed to Total Ionization Dose (TID). Additionally, the integration of the device into a test platform developed for SEE characterization is presented, along with the results of the device’s resistance to high-energy ion impacts. The ADC features a pipeline architecture, operates at 80 MSps, and is specifically designed for use with scientific instrumentation in space applications and environments exposed to radiation.

   3. Radiation Tolerance of the TOFHIR2 ASIC for the CMS/CERN Timing Detector

      Edgar Albuquerque, Alessio Boletti, Ricardo Bugalho, Tahereh Niknejad, Luís Bica Oliveira, Nuno Oliveira, José Silva, João Varela

      Abstract

      The CMS detector is set to be upgraded for the HL-LHC proton collider at CERN with the addition of a MIP Timing Detector (MTD). The MTD will feature barrel and endcap timing layers, BTL and ETL, to enable precise timing measurements of charged particles. The BTL sensors use LYSO:Ce scintillation crystals coupled to SiPMs and TOFHIR2 ASICs for front-end readout. Over the HL-LHC's lifetime, the system is expected to achieve a timing resolution of 30–60 ps for MIP signals at a rate of 2.5 Mhit/s per channel. During its operation, the detector is exposed to a large flux of particles. As a consequence, the TOFHIR2 chip must be resistant to the expected total ionization dose TID (29 kGray) and to the integrated particle fluence (2 × 10e14 neq/cm²) in the BTL.

      In this paper, we present an overview of the TOFHIR2 requirements and design, and of the measurements performed with TOFHIR2 ASICs with emphasis on the radiation resistance. The measurements of TOFHIR2 associated to sensor modules were performed in different test setups using internal test pulses or blue and UV laser pulses emulating the signals expected in the experiment. Extensive radiation tests, including x-rays and heavy ions, confirmed that TOFHIR2 remains unaffected by the radiation environment throughout the experiment's lifetime.

   4. Eliminating Measured Radiation Effects to Go for FM-Level Mixed Signal Design

      Sebastian Millner, Volker Lück

      Abstract

      By further optimizing the radiation hardness, the radiation effects that were measured in the first prototype of our 180 nm X-FAB ASIC flight model were mitigated or even completely eliminated. These effects include a fatal drift during total dose and single event transients on analog outputs and a cumulative destructive event when irradiated with high-energy particles. We describe developed measurement setups, test results, methods of analysis and the solutions found for the issues.

6. Reusable Design Libraries

   1. Frontmatter

   2. PROMISE, PROgrammable MIxed Signal ASIC Electronics Electrical Characterisation

      Dimitrios Baramilis, Nikolaos Vasileiadis, Kostas Makris, Olga Dokianaki, Constantin Papadas, Philippe Ayzac

      Abstract

      The aim of this communication is to present the electrical characterization results of the ADC that was implemented through the European union’s Horizon 2020 research and innovation program PROMISE.

   3. Characterization and Measurement of the SET Pulse Duration of the DARE65T Standard Cell Library

      Laurent Berti, Bastien Vignon, El Hafed Boufouss, Maxim Gorbunov, Zheyi Li, Marcel van de Burgwal

      Abstract

      A novel test structure enables simultaneous measurement of SET cross-sections and pulse widths in 65 nm standard cells, validating SET filter effectiveness and supporting optimized hardening strategies for space-grade digital circuits.

   4. Radiation Hardening by Design Concepts for 7-nm FinFET Technologies

      Maxim Gorbunov, Alican Caglar, Sivaramakrishnan Hariharakrishnan, Evgenii Timokhin, Marcel van de Burgwal, Laurent Berti, Geert Thys, Nidhish Gaur

      Abstract

      For ultra deep sub-micron technologies, charge sharing affects areas beyond the standard cell dimensions. Scaling up cells to ensure no charge sharing occurs inside therefore would have a major negative impact on area efficiency. We propose a D-flip-flop based on the principles of multi-bit flip-flops with integrated majority voters for the Triple Modular Redundancy (TMR) scheme, where the internal triplicated elements respect the critical spacing requirement and the cell can be used as a intrinsic rad-hard cell that requires no additional radiation mitigation on system level. We discuss the design trade-offs and compare the performance parameters of single- and multi-bit D-flip-flops from the standard library with the designed 2-bit TMR and 1-bit (Dual Interlocked Cell-based (DICE) DFFs.

   5. Evaluation of the DARE65T Platform: Technology Study, IP Library Development and Demonstrator ASIC Design

      Marcel van de Burgwal, Maxim Gorbunov, Laurent Berti, Lucas Tambara

      Abstract

      The 65nm CMOS node is used for the development of DARE65T, an aerospace grade ASIC platform that can be used to design radiation-hardened-by-design ASICs with commercial foundry technology. The platform is composed of a range of IP libraries including standard cell, IO, SRAMs, as well as mixed signal IPs including PLL, current/voltage reference and ADC. All IPs are evaluated under irradiation by means of two different test vehicles, and a functional demonstrator ASIC is presented as a proof of platform readiness for flight model ASICs.

7. Backmatter