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EUROGRAPHICS workshops on Graphics hardware have now become an established forum for an exchange of information con­ cerning the latest developments in this field of growing importance. The first workshop took place during EG'86 in Lisbon. All parti­ cipants in this event considered it a very rewarding workshop to be repeated at future EG conferences. This view was reinforced at the EG'87 Hardware Workshop in Amsterdam which firmly esta­ blished the need for and a high interest in such a colloquium of technical discussion in this specialist area within the annual EG conference. The third EG Hardware Workshop took place in Nice in 1988 and this volume is a record of the fourth workshop at EG'89 in Hamburg. The material in this book contains papers representing a com­ prehensive record of the contributions to the 1989 workshop. The first part considers Algorithms and Architectures of graphics systems. These papers discuss the broader issues of system design, without necessarily raising issues concerning the details of the implementation. The second part on Systems describes hardware solutions and realisations of machines dedicated to graphics processing. Many of these contributions make important references to algorithmic and architectural issues as well, but there is now a greater emphasis on realisation. Indeed many VLSI designs are described.



Algorithms and Architectures


Towards a Taxonomy for Display Processors

Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The subsystem performing the pixel processing is called display processor.
In the paper a model for the display processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as the key functions of the display processor. The timing model is expressed in an inequation being fundamental for all display processor architectures.
On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, architecture and performance.
The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System.
Investigation of existing display processor architectures on the basis of the developed taxonomy revealed a potential new architecture. This architecture partitions the image generation process in image space and employs a tree topology.
Bengt-Olaf Schneider

A Hardware Algorithm for Fast Realistic Image Synthesis

A VLSI oriented algorithm, for the implementation of a generalized two-pass radiosity method is presented. The method allows any reflection behavior, varying from purely diffuse to perfect mirroring. Moreover, objects may be defined in terms of curved (Bezier) surfaces. All computations in the pre- and postprocess are similar and ray-tracing based, consequently a single architecture can be devised for both passes. This architecture, when built on ray-rotating and ray-tracing pipelined processors such as Cordics, results in a very high throughput VLSI implementation of the proposed generalized two-pass procedure.
A. C. Yilmaz, S. Hagestein, E. Deprettere, P. Dewilde

The HERO Algorithm for Ray-Tracing Octrees

An algorithm is presented for rapid traversal of octree data structures, in order to enhance the speed of ray tracing for scenes of high complexity. At each level of the octree, the algorithm generates the addresses of child voxels in the order they are penetrated by the ray. This requires only a few arithmetic operations and simple logical operations. A depth-first search of the tree is used to yield the first terminal voxel hit by the ray, thus hidden objects are not processed. The algorithm is designed specifically for implementation as HERO: A Hardware Enhancer for Ray-tracing Octrees.
Mark Agate, Richard L. Grimsdale, Paul F. Lister

A VLSI Architecture for Anti-Aliasing

Computer-synthesized images exhibit the typical artifacts of raster displays, called aliasing, rastering, staircasing or thejaggies”. Display of an image on a raster CRT requires the sampling the two dimensional image signal I(x,y) to obtain a pixel-based description of intensity. Unfortinately, this sampling process treates the pixel as a mathematical point and the point sampling of an unfiltered object is never correct at any resolution. Aliasing effects (spatial and temporal) are due to undersampling of the image signal. Spatial aliasing occurs when images contain frequencies greater than one half the spatial sampling frequency. Lines that should be straight appear jagged, very small objects may not be visible, portions of long thin objects may disappear.
Claudia Romanova, Ulrich Wagner

PS: Polygon Streams A Distributed Architecture for Incremental Computation Applied to Graphics

Polygon Streams is a distributed system with multiple processors and strictly local communication. A unique custom VLSI chip that constitutes an independent processing module forms a stage of the PS pipeline. The number of these modules in PS is a variable that is determined by the application. PS features a modular architecture, multi-ported on-chip memory, bit-serial arithmetic, and a pipeline whose computation can be dynamically configured. The PS design closely subscribes to the system characteristics favored by VLSI.
The task of scan conversion for rendering computer graphics images on raster scan displays is very intensive in computation and pixel information access. It is very coherent and suitable, however, for forward difference algorithms. The discrete and regular layout of the raster display, in conjunction with the largely local effect of a pixel on an image, make rendering amenable to parallel architectures with localized memory and communication. These are precisely the attributes favored by VLSI and typical of PS.
A modification of the Digital Differential Analyzer (DDA) is implemented to Gouraud Shade and depth buffer convex polygons at high speeds. The scan conversion task is distributed over the processors to efficiently subdivide the image space and maximize concurrency of processor operation.
A study of the tradeoffs and architectural choices of the PS reveal the merits and deficits of the PS approach in comparison with Pixel-Planes, SLAMs, Super-Buffers, and SAGE.
Rajiv Gupta

A Generalised Parallel Architecture for Image Based Algorithms

Real time image generation and image understanding require levels of computing power, that are beyond that available from conventional sequential machines. Current commercially available systems aimed at this area make use of special purpose hardware to achieve the necessary throughput, but these systems can only achieve their performance for a restricted set of algorithms that are implemented in the hardware. A programmable general purpose parallel machine offers the possibility to achieve the required performance without restricting the choice of algorithm.
G. J. Vaudin, G. R. Nudd, T. J. Atherton, S. C. Clippingdale, N. D. Francis, R. M. Howarth, D. J. Kerbyson, R. A. Packwood, D. Walton

Two-level Pipelining of Systolic Array Graphics Engines

In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic array graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic array graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic array graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graph-theoretic approach. Furthermore, we characterize the architectures which can be improved by pipelined functional units.
J. A. K. S. Jayasinghe, O. E. Herrmann



A Dedicated Graphics Processor SIGHT-2

SIGHT-2 is a multiprocessor system that is intended to efficiently execute the ray tracing algorithm. To achieve high efficiency, three kinds of parallel execution mechanisms; (i) a multiprocessor configuration, (ii) a parallel execution of three dimensional vector operations, and (iii) functionally distributed parallel processing are introduced. Owing to the latter two techniques, each processing element (PE) has the ability to execute the standard ray tracing algorithm 10 times faster than a VAX11/780 with a floating point accelerator. In the present configuration, SIGHT-2 utilizes 16 PEs, which results in a peak power of 66.72 MFLOPS / 133.28 MIPS. During ray tracing, the efficiency of each PE is over 99% under static load balancing.
In this paper, SIGHT-2 system architecture, its PE configuration, and VLSIs design are discussed. The system performance is also discussed.
Masaharu Yoshida, Tadashi Naruse, Tokiichiro Takahashi

Viewing and Rendering Processor for a Volume Visualization System

The architecture and the hardware realization of the 3D Viewing and Rendering Processor is presented. This processor is a component of the Cube architecture, developed primarily for volume visualization. The processor generates 2D shaded orthographic, parallel, and perspective projections of the volumetric image of n 3 voxels in O(n 2 logn ) time. This performance is attributed to a unique skewed memory organization, a special ray projection bus, an extended viewing architecture, and a new congradient shading technique. A reduced-resolution prototype has been realized in hardware using printed circuit board technology and has been running in true real time. Currently, a VLSI version of the prototype is being tested.
A. Kaufman, R. Bakalash, D. Cohen

Presentation of the Cubi9000: A Graphics System based on Inmos T800 Transputers

The Cubi9000 family includes a range of products from the 3D graphics terminal up to the 3D graphics workstation. The Cubi9000 when configured as a 3D graphics terminal connects to a host computer via a parallel interface from Digital Equipment Corporation. The Cubi9000 configured as workstation includes a UNK2 based mini-computer with a 32 bit microprocessor, mass memory, device handlers (mouse, tablets, encoders) and communication drivers to external systems.
France Glemot

A Virtual Memory System Organization for Bit-Mapped Graphics Displays

Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an environment that consists of a hierarchy of resizable windows. The concept of virtual memory has been applied with the organization of the virtual to physical address spaces having a unique mapping that fits the organization of a bit-mapped graphics memory display.
CR Categories and Subject Descriptors: I.3.1 [Computer Graphics]: Hardware Architectures — raster display devices; 1.3.3 [Computer Graphics]: Picture/Image Generation — display algorithms.
Anthony C. Barkans

A Real-Time Raster Scan Display for 3-D Graphics

This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15•106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. The performance of the geometry processor, which is responsible for the geometrical transformations, the 3-d clipping and the perspective projection, will exceed 100,000 triangle shaped polygons.
Following a survey of the entire 3-d real-time system, we will describe architectural details of the rendering processor. Finally, the main features enabled by the architecture are highlighted.
D. Jackèl, H. Günther, B. Herwig, H. Rüsseler

The Graphics Unit of the INTEL I80860

The Intel I80860 is a very powerful RISC processor, designed for applications that require a large amount of floating point and integer calculations. Additionally it supports graphics applications with a Graphics hardware unit. The aim of this article is to investigate, for which application this unit is useful and whether the results obtained by the help of this unit are better as with standard C or assembly implementations of the same algorithm.
Ulrich Kursawe

A Chinese-Character and Graphics Workstation

This paper introduces the design approaches of a Chinese-character and graphics workstation DGS-8000 which has been developed at the Computer Graphics Research Laboratory, Department of Computer Science and Engineering, Zhejiang University. The specifications, architecture, Chinese-character processing environment and working modes of the workstation are described. Especially the I/O interface with the host computer, the processor unit, the graphics generation and display unit, Chinese-character operating system and some main input modes of Chinese-character codes are introduced in detail.
Shi Jiaoying, Huang Jianfeng, Liu Liancai, Hu Jingyi

A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System

Today’s workstation users demand high computational performance combined with powerful graphics and a comfortable window system. Existing and forthcoming standards like GKS-3D, PHIGS/PHIGS+, X Window System, and PEX have to be supported optimally.
Thomas Haaker, Harald Selzer, Hans Joseph


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