Advances in Rapid Thermal and Integrated Processing

Today, ULSI (ultra large scale integration) in silicon-based mass-produced integrated circuits (ICs) has its state-of-the-art representatives in microprocessors such as Intel’s Pentium or, even more powerful, the PowerPC, jointly designed by Apple, IBM and Motorola. Both products were originally designed in a 0.5 pm, 3.3 Volt CMOS (complimentary metal oxide semiconductor) technology. The Power PC contains 3.6 million transistors onto a chip, measuring 196 mm² [1]. In the course of 1995 the line width has been further reduced to 0.35 pm for the development of processors with some 5 metal levels, such as the Pentium Pro (or P6) processor, as part of a series of continuously shrinking microelectronics, which started after the first planar single transistor in 1959 [2].

The development of rapid thermal processing (RTP) techniques for the fabrication of advanced electronic devices requires a detailed understanding of the thermal radiative properties of semiconductor wafers. Fig. 1 illustrates the main reasons to be interested in these properties:

All objects at the same temperature do not radiate energy the same way. In 1860 Kirchhoff introduced the powerful new concept: that a suitably shaped cavity with a small opening radiates energy solely as a function of temperature [1]. In 1896 Wien published his theoretical treatment of blackbody radiation based purely on thermodynamics [2]. Wien correctly described the peak blackbody wavelengths as a function of temperature, but failed to produce an accurate mathematical model for blackbody radiation. On December 14, 1900, in Berlin, Max Planck suggested the following equation to describe blackbody radiation: where I is the intensity of the emitted light, c is the speed of light, λ is the wavelength of light, and h is the Planck constant. The Planck constant, h, is equal to the very tiny quantity, 6.6 × 10^-34 Joule seconds. The revolutionary nature of the Planck equation comes from this constant. It implies a definite lower limit on the discrete energy, or quantum jumps, or “bands” that are allowed by the atoms that emit the radiation.

“The future of RTP depends (...) on improving temperature control (...) in RTP equipments” [1].”Implementation of single wafer RTP systems into microelectronics fabrication will require an improvement of the existing (...) control technology for these systems” [2]. Obviously these two citations have a very similar meaning. They both come from review papers presented at two international meetings. The only difference is that the first meeting was held in 1987, and the second in 1994. Obviously, process control for RTP is still an important issue. In the following, after a brief historical presentation, we will develop the background associated with RTP process control, together with the state-of-the-art. The specific issue of temperature measurement is presented in Chapter 3.

State-of-the-art semiconductor technologies employ thermal processing steps for various anneal, oxidation, and chemical vapor deposition (CVD) processes. Most of these fabrication processes have been dominated by hot-wall batch furnaces. Many other unit processes, however, are already performed in single-wafer processors. These include plasma etch, plasma-enhanced dielectric deposition, metal deposition, ion implantation, and microlithography. The advantages of single-wafer processing have been discussed elsewhere [1]. They have been primarily related to enhanced control of processing individual wafers, particularly as the diameter of silicon wafers has increased to 200 mm.

According to the Semiconductor Industry Association (SIA) roadmap, gate dielectrics for forthcoming 0.25 µm technology will be as thin as 4.5–7.4 nm. Device scaling for future technologies, and low power applications (i.e., wireless, laptop) will further drive gate dielectric thicknesses down to 3.5 nm, close to the oxide tunneling limit. The electrical properties, reliability and manufacturability of such thin dielectrics are of enormous importance for the success of future technologies. In this chapter I will discuss rapid thermal oxidation (RTO) of oxides and oxynitrides using O₂ and N₂O, respectively. I will compare and contrast current furnace oxidation technology with RTO technology, and come to the conclusion that there are several advantages to growing dielectrics at the higher temperatures that RTO can achieve. However, RTO must mature to be competitive with furnace oxidation.

Scaling of ULSI device dimensions results in decreasing gate dielectric thickness. Currently manufactured integrated circuits obey 0.5 µm design rules, with gate dielectrics approximately 10 nm thick. 0.25 µm technology, now in research, will require 7 nm gate dielectrics. Gates will further shrink to 4.5 nm for 0.18 µm technology by the turn of the century. It is important to understand that as the gate dielectric thickness decreases, the Si/SiO₂ interfacial region becomes a more significant part of the gate dielectric. This makes pre-gate dielectric surface preparation one of the most critical steps in integrated circuit manufacturing [1–5].

As pointed out on numerous occasions in this book, minimisation of the thermal budget of ULSI electronic devices during processing, is very much a necessity. Consequently, in addition to reducing or eliminating unnecessary heat-up and cool-down steps, various low temperature techniques are also being explored that involve substitute sources of energy for the deposition and growth chemistry. Over the years, photo-induced processing has in particular received considerable attention [1–3]. One advantage of photoprocessing is that the surface is not subjected to damaging ionic bombardment which can be the case in plasma assisted systems [4,5].

With the shift towards single wafer cluster tools and reduced thermal budgets, rapid thermal processing (RTP) is becoming an increasingly important microelectronics manufacturing technology for oxidation, implant annealing, and silicidation [1]. The continued evolution towards shallower junctions and thinner oxides is likely to further drive thermal processes toward RTP and away from furnaces. However, for this transition to take place, RTP must overcome current limitations in terms of temperature measurement and spatial temperature control, as well as satisfy increasingly tight performance specifications [2] . Accurate temperature measurements are needed to avoid wafer to wafer drift and to serve as input to lamp feedback control schemes minimizing spatial temperature variations.

When RTP was introduced as a promising technology step for IC fabrication, one was interested in the first place in its flexibility for the high temperature range. Meanwhile, RTP has been introduced in research for almost every temperature treatment. Whereas the high temperature range is still extremely attractive for implant activation and gate oxidation, possible applications in the silicide and metallization areas have widened the temperature range of interest down to the very limits for which radiation heating can still be envisioned, being typically 400 °C.

At Stanford University we have developed concepts of a programmable factory, an alternative Adaptable Manufacturing Systems (AMS) approach to IC fabrication, which may offer more economical small or large scale production, higher flexibility to accommodate many products on several processes, and faster turnaround to hasten product innovation [1–3]. This approach is based on a new generation of single-wafer, flexible, multifunctional equipment with extensive use of computer integrated manufacturing (CIM) to further enhance the flexibility. In this approach programmable equipment quickly processes one semiconductor wafer at a time, performs several process steps insitu in contrast to the conventional alternative of slowly processing many wafers simultaneously and one step per equipment [1–3]. Single-wafer processing facilitates the use of in-situ monitoring and real-time control. Extensive use of CIM for specification, monitoring, control, and information management should make switching between processes faster and more reliable, should increase the ease by which large numbers of different products could simultaneously be routed and tracked through the factory, and should maximize equipment utilization.

Developing clean and renewable energy resources has become one of the most important tasks assigned to modern science and technology. The reasons for this strong motivation are the limitation of the conventional resources and the necessity to stop air pollution resulting from the mass consumption of fossil fuels. Solar energy is the only energy which guarantees a sustainable development. This energy is received by the earth in almost abundant quantities and will be available for extremly long periods of time. The amount of solar radiation energy striking the earth is approximately l0⁴ times as much as the present worldwide energy consumption. Even in densely populated areas like Great Britain or Germany this energy is still l0²-times larger than the power demand of the population in these countries. Among a wide variety of renewable energy projects in progress, photovoltaics is one of the most promising ones for electric energy generation. At present the costs of photovoltaic energy converters, i.e. solar cell modules, is a major obstacle for their application. To achieve a price reduction, tremendous R&D efforts have been made in a wide variety of technical fields concerning solar cell materials, cell design, and the potentials of cost lowering by mass production of photovoltaic systems. However, another cost reduction by a factor of five is required to approach the present conventional electricity price [1].

The present contribution gives some insight into equipment design. It is not possible to cover everything concerning design. Therefore, this contribution is mainly focused on the design of MESC (Modular Equipment Standards Committee) compatible cluster tools for RTP applications which is followed by some remarks concerning the scale-up in terms of wafer size. Due to the fact, that the design of the cluster modules was started from the basic design of the stand-alone RTP—system, a brief description of this chamber will be given prior to more specific considerations about cluster design.

Epitaxy of Si on Si substrates by CVD is an old technique. Developed to improve the performance of bipolar transistors and integrated circuits, it is finding increasing application in CMOS circuits as well. In both cases an epitaxial layer is grown on top of a substrate to contain the active devices. Shrinking device dimensions, laterally as well as vertically, require small transition widths for a change in dopant type or concentration and traditional silicon-epi growth with its high deposition temperatures is becoming more and more incompatible with modern wafer processing. Outdiffusion of dopants and autodoping preclude the use of conventional epi in tailoring dopant profiles in e.g. the base of a bipolar transistor.

Since the introduction of the first commercially available Rapid Thermal Processing (RTP) systems some twenty years ago, it has been claimed that RTP technology is required for manufacturing processes. However, until recently RTP technology has been almost ignored by manufacturing due to low reproducibility in processing. The main reason for this situation is the fact that an alternative processing technology was widely available: the conventional batch processing furnace.

Rapid Thermal Processing (RTP) in the Compound Semiconductor technology has had a significant impact in making such a technology reliable and manufactureable. Since 1980 [1] RTP has been applied to achieving control of doping profiles, achieving implant activation and the application of advanced metallization systems. Since 1990 [2], RTP in the form of pulsed excimer laser processing has been applied to molecular beam epitaxial growth (MBE) for the development of high resistivity buffer lasers and for achieving the heterostructures necessary for high electron mobility transistors (HEMTs). The emphasis in the present paper is to review the GaAs device technology, the material problems and device structures and to show that RTP has removed key material problems which were bottlenecks in achieving a fabrication process which is reliable and high yield.