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CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.
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The degradation is caused by the coaction of NBTI and PBTI but is mostly contributed by NBTI for the 65-nm technology, which uses silicon dioxide-based transistors. PBTI is only considered to be crucial for the transistors with high-k materials, mostly applied for sub-40-nm technologies.
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- Ageing-Aware Logic Synthesis
- Chapter 5