Ageing of Integrated Circuits

This chapter starts with a brief review on the basic ageing phenomenon and the working principles and structures of MOSFET transistors. It then presents the unwanted but unavoidable oxide defects leading to charge traps and presents activation mechanisms. These defects can lead to a variety of known ageing effects, such as negative/positive bias instability, hot carrier degradation (alias hot carrier injection), random telegraph noise and time-dependent dielectric breakdown. The impact of these effects onto the individual transistor and consequentially the entire integrated circuit are then discussed. The remainder of this chapter reviews various quantitative ageing models. It starts with the fundamental explicit switching trap models, which individually describe each of the many traps inside every transistor oxide layer. The more abstract stochastic trap representation as capture-emission time maps is leading to practical models at the TCAD and electrical level, respectively. Based on these fundamental models, there are various further abstractions, bridging the gap between the nanosecond timescales, integrated circuits work at and the years or decades, over which circuit ageing is taking place. Analytic models offer a simple ageing assessment by making several worst-case assumptions, usually leading to a vast overestimation. CET map abstractions allow a realistic assessment of the ageing of small circuits such as individual critical paths. Finally, trap centric models enable several ways of accelerating ageing models. The most sophisticated ones can process millions of transistors over years of lifetime with a reasonable accuracy.

Bias temperature instability (BTI) is recognised as the primary parametric failure mechanism in nanometre integrated circuits (ICs). Due to the BTI-induced increase in transistor threshold voltage, circuit performance can degrade noticeably over time. If this induced performance degradation exceeds circuit time margins, it may lead to circuit failure and reduce lifetime of electronic systems. In addition, IC susceptibility to soft errors induced by energetic particles is aggravated by BTI ageing, and so resilience of circuits initially robust against these events decreases over time. In order to assess the impact of BTI ageing on IC reliability, it is of utmost importance to evaluate its impact on both IC performance degradation and soft error rate. This chapter describes methodologies to evaluate BTI ageing accurately and presents results on its impact on performance and soft error rate of combinational circuits and storage elements. The presented results can help designers make the right choices when they are called to design ICs featuring high reliability for their whole lifetime.

In this chapter, we will aim to reverse the aging stress on the functional units of the processor by applying high-level workloads as anti-aging patterns into the stressed component. We present a time-redundant technique to mitigate negative and positive bias temperature instability (NBTI/PBTI) aging effects on the combinational units of a processor. We have analysed the sources and effects of aging from the device level to the instruction set architecture (ISA) level and have found that an application may stress the critical paths in such a way that the combinational circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be extended by applying balanced stress patterns at a higher level of abstraction and during the idle time of a processor system.

As CMOS technology scales down, ageing-induced negative-bias temperature instability (NBTI) becomes more pronounced. The impact of NBTI on memory elements of digital circuits is crucial, in particular, in static random-access memory (SRAM) as it is always subject to ageing for whatever value is stored in an SRAM cell. Moreover, the prolonged storage of the same bit patterns in an SRAM can cause asymmetric NBTI stress, which is manifested by the threshold voltage drifts of pMOS transistors. These long-term ageing threshold voltage drifts degrade the static noise margin (SNM) of SRAM as memory. The degradation in SNM due to asymmetric NBTI stress can lead to read stability issues and potentially cause failures. Furthermore, the impact of NBTI on SRAM is not only limited to its usage as a memory but also as a hardware security primitive, namely, SRAM physical unclonable function (SRAM-PUF). The random and unique start-up values (SUVs) of SRAM-PUF can be used as a cryptographic key. Nevertheless, asymmetric NBTI stress may cause errors in SUVs. As the error in the SUVs increases resulting in an increasing area overhead of error correction code (ECC) which is needed to generate an error-free cryptographic key. Following the aforementioned reliability issues, this chapter presents two case studies of ageing mitigation techniques for SRAM as memory and PUF, respectively.

CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.

Process, voltage, temperature and ageing variations have become important issues in nanometre technology nodes, and thus on-chip accurate reliability and performance monitors have become necessary for adaptive compensation schemes. This chapter presents up-to-date state-of-the-art performance and reliability monitors, insertion methodology and experimental results of different monitors used for process and environment variations as well as ageing compensation. Voltage and frequency scaling techniques are combined with monitors to ensure fault-free operation. Measurements and simulations were performed on large sample sets for varied range of process, voltages, temperatures and ageing to argument on the choice of paths to be monitored and to illustrate adaptive compensation techniques.

Static random access memories (SRAMs) in nanometre technologies undergo reliability degradation due to the increased process variations but also due to various aging mechanisms. Bias temperature instability (BTI) and hot carrier injection (HCI) phenomena are highly accused of the aging-related reliability reduction. This degradation is getting worse under excess stress conditions (high operating temperature and voltage levels). Aging phenomena significantly affect the performance characteristics of SRAMs since they affect among others speed, operating voltages, memory cells’ noise margins and sense amplifiers’ input offset voltage. Excessive performance degradation due to aging in an SRAM will lead to failures generation. Traditionally, designers use guard bands; extra margins are considered to guarantee that the memory will operate correctly during its lifetime. However, this approach negatively influences the performance of the circuit since it affects speed, power consumption, area and possibly the yield. Thus, it is imperative to develop aging-tolerant design techniques that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation.

Aggressive technology shrinking has increased the sensitivity of integrated circuits in terms of devices ageing. As a result, the performance of a CMOS device will degrade significantly over time and, therefore, results in the delay faults. In situ delay fault monitoring schemes have been proposed to ensure the reliability of an IC during its lifetime. Such schemes are usually based on the application of ageing sensors to predict ageing-induced failures of a circuit and react accordingly. Traditional ageing sensors are implemented on the near-critical paths, which are considered as the most vulnerable paths to delay faults caused by performance degradation. However, today’s complex designs and technology node shrinking have enhanced the number of near- and potential critical paths that need to be monitored. This means the in situ delay fault monitoring approaches are becoming very expensive and may be infeasible. This chapter introduces a state-of-the-art in situ delay monitor called Differential Multiple Error Detection Sensor (DMEDS). The chapter presents a case study to demonstrate how the DMEDS monitors multiple paths simultaneously, and it discusses the advantages and disadvantages of this proposed approach compared with the traditional techniques.