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2017 | OriginalPaper | Buchkapitel

8. An Overview on Memristor-Based Non-volatile LUT of an FPGA

verfasst von : T. Nandha Kumar

Erschienen in: Frontiers in Electronic Technologies

Verlag: Springer Singapore

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Abstract

This paper presents detailed over view of four different novel memristor-based nano-crossbar structures that are employed for designing a Non-Volatile Look-Up Table (NVLUT) of a Field Programmable Gate Array (FPGA) with particular focus on efficient READ and WRITE operations; techniques to overcome the effect sneak path current on unselected memristors. Cross-point memory array structure, MOS accessed memory array structure, Memory array structure with transistors at BL and Columns isolated memory array structure are the different structures considered in this paper. The paper analyzes in detail about the LUT structures and their WRITE and READ operations. Also the analysis on the SPICE simulation results of the READ and WRITE delay, energy dissipation and energy delay product of four LUT structures are presented. Among the LUT structures, Columns isolated memory array structure seems to be potential candidate for NVLUT as it eliminates the effect of sneak path current on the unselected memristors. Also it showed a fast WRITE time, significantly reduced READ power dissipation and no power dissipation in the stand-by mode. In addition, it eliminates the write half-select issue. Moreover, it prevents the data integrity when compared with other structures as this structure has better controllability of the NSPs for the unselected memristors.

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Literatur
1.
Zurück zum Zitat H.A.F. Almurib, T.N. Kumar, F. Lombardi, A single-configuration method for application-dependent testing of SRAM-based FPGA interconnects, in Proceedings of the 20th IEEE Asian Test Symposium, New Delhi (2011), pp. 444–450 H.A.F. Almurib, T.N. Kumar, F. Lombardi, A single-configuration method for application-dependent testing of SRAM-based FPGA interconnects, in Proceedings of the 20th IEEE Asian Test Symposium, New Delhi (2011), pp. 444–450
2.
Zurück zum Zitat T. Nandha Kumar, F. Lombardi A novel heuristic method for application dependent testing of a FPGA interconnect. IEEE Trans. Comput. 16(1), 163–172 (2013) T. Nandha Kumar, F. Lombardi A novel heuristic method for application dependent testing of a FPGA interconnect. IEEE Trans. Comput. 16(1), 163–172 (2013)
3.
Zurück zum Zitat K.J. Han et al., A novel flash-based FPGA technology with deep trench isolation, in 22nd IEEE Non-Volatile Semiconductor Memory Workshop (2007), pp. 32–33 K.J. Han et al., A novel flash-based FPGA technology with deep trench isolation, in 22nd IEEE Non-Volatile Semiconductor Memory Workshop (2007), pp. 32–33
5.
Zurück zum Zitat T.N. Kumar, H.A.F. Almurib, F. Lombardi, On the operational features and performance of a memristor-based cell for a LUT of an FPGA, in Proceedings of the13th IEEE International Conference on Nanotechnology (2013), pp. 71–76 T.N. Kumar, H.A.F. Almurib, F. Lombardi, On the operational features and performance of a memristor-based cell for a LUT of an FPGA, in Proceedings of the13th IEEE International Conference on Nanotechnology (2013), pp. 71–76
6.
Zurück zum Zitat L.O. Chua, Memristor—the missing circuit element. IEEE Trans. Circ. Theory ct-18(5), 507–519 (1971) L.O. Chua, Memristor—the missing circuit element. IEEE Trans. Circ. Theory ct-18(5), 507–519 (1971)
7.
Zurück zum Zitat D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor found. Nature 453, 80–83 (2008)CrossRef D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor found. Nature 453, 80–83 (2008)CrossRef
8.
Zurück zum Zitat J. Cong, B. Xiao, mrFPGA: a novel FPGA scheme with memristor-based reconfiguration, in Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (2011), pp. 1–8 J. Cong, B. Xiao, mrFPGA: a novel FPGA scheme with memristor-based reconfiguration, in Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (2011), pp. 1–8
9.
Zurück zum Zitat S. Tanachutiwat, M. Liu, W. Wang, FPGA Based on Integration of CMOS and RRAM. IEEE Trans. Very Large Scale Integr. VLSI Syst. 19(11), 2023–2032 (2011)CrossRef S. Tanachutiwat, M. Liu, W. Wang, FPGA Based on Integration of CMOS and RRAM. IEEE Trans. Very Large Scale Integr. VLSI Syst. 19(11), 2023–2032 (2011)CrossRef
10.
Zurück zum Zitat Y. Ho, G.M. Huang, P. Li, Dynamical properties and design analysis for nonvolatile memristor memories, in IEEE Trans. Circ. Syst. I 58(4) (2011) Y. Ho, G.M. Huang, P. Li, Dynamical properties and design analysis for nonvolatile memristor memories, in IEEE Trans. Circ. Syst. I 58(4) (2011)
11.
Zurück zum Zitat C. Xu, X. Dong, N.P. Jouppi, Y. Xie, Design implications of memristor-based RRAM cross-point structures, in Proceedings of the Design, Automation and Test in Europe (2011), pp. 1–6 C. Xu, X. Dong, N.P. Jouppi, Y. Xie, Design implications of memristor-based RRAM cross-point structures, in Proceedings of the Design, Automation and Test in Europe (2011), pp. 1–6
12.
Zurück zum Zitat A. Chen, Accessibility of nano-crossbar arrays of resistive switching devices, in Proceedings of the IEEE International Conference on Nanotechnology (2011), pp. 1767–1771 A. Chen, Accessibility of nano-crossbar arrays of resistive switching devices, in Proceedings of the IEEE International Conference on Nanotechnology (2011), pp. 1767–1771
13.
Zurück zum Zitat I.E. Ebong, P. Mazumder, Self-controlled writing and erasing in a memristor crossbar memory, in IEEE Transactions on Nanotechnology, vol. 10, no. 6 (2011) I.E. Ebong, P. Mazumder, Self-controlled writing and erasing in a memristor crossbar memory, in IEEE Transactions on Nanotechnology, vol. 10, no. 6 (2011)
14.
Zurück zum Zitat J. Liang, H.-S. P. Wong, Cross-point memory array without cell selectors—device characteristics and data storage pattern dependencies. IEEE Trans. Electron Dev. 57(10) (2010) J. Liang, H.-S. P. Wong, Cross-point memory array without cell selectors—device characteristics and data storage pattern dependencies. IEEE Trans. Electron Dev. 57(10) (2010)
15.
Zurück zum Zitat H.A.F. Almurib, T.N, Kumar, F. Lombardi, A memristor-based LUT for FPGAs, in Proceedings of the 9th IEEE International Conference on Nano/Micro Engineered and Molecular System IEEE-NEMS (2014), pp. 448–453 H.A.F. Almurib, T.N, Kumar, F. Lombardi, A memristor-based LUT for FPGAs, in Proceedings of the 9th IEEE International Conference on Nano/Micro Engineered and Molecular System IEEE-NEMS (2014), pp. 448–453
16.
Zurück zum Zitat T.N, Kumar, H.A.F. Almurib, F. Lombardi, A novel design of a memristor-based look-up table (LUT) for FPGA, in IEEE Asia Pacific Conference on Circuits and Systems (2014) T.N, Kumar, H.A.F. Almurib, F. Lombardi, A novel design of a memristor-based look-up table (LUT) for FPGA, in IEEE Asia Pacific Conference on Circuits and Systems (2014)
17.
Zurück zum Zitat H.A.F. Almurib, T. Nandha Kumar, F. Lombardi, Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays. IET Circ. Dev. Syst. (2016) H.A.F. Almurib, T. Nandha Kumar, F. Lombardi, Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays. IET Circ. Dev. Syst. (2016)
18.
Zurück zum Zitat T. Nandha Kumar, H.A.F. Almurib, F. Lombardi, Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs. Integr. VLSI J. (2016). Elsevier T. Nandha Kumar, H.A.F. Almurib, F. Lombardi, Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs. Integr. VLSI J. (2016). Elsevier
19.
Zurück zum Zitat P.W.C. Ho, T. Nandha Kumar, H. Abbas, Configurable memristive logic block for memristive-based FPGA architectures. Integr. VLSI J. (2016). Elsevier P.W.C. Ho, T. Nandha Kumar, H. Abbas, Configurable memristive logic block for memristive-based FPGA architectures. Integr. VLSI J. (2016). Elsevier
20.
Zurück zum Zitat P.W.C. Ho, H.A. Mohamed, T. Nandha Kumar, One-bit non-volatile memory cell using memristor and transmission gates, in IEEE International Conference on Electronic Design (ICED 2014), Malaysia (2014), pp. 244–248 P.W.C. Ho, H.A. Mohamed, T. Nandha Kumar, One-bit non-volatile memory cell using memristor and transmission gates, in IEEE International Conference on Electronic Design (ICED 2014), Malaysia (2014), pp. 244–248
21.
Zurück zum Zitat P. Junsangsri, F. Lombardi, A novel hybrid design of a memory cell using a memristor and ambipolar transistors, in Proceedings of the 11th IEEE International Conference on Nanotechnology (2011) P. Junsangsri, F. Lombardi, A novel hybrid design of a memory cell using a memristor and ambipolar transistors, in Proceedings of the 11th IEEE International Conference on Nanotechnology (2011)
22.
Zurück zum Zitat A. Chen, Accessibility of nano-crossbar arrays of resistive switching devices, in IEEE International Conference on Nanotechnology (2011) A. Chen, Accessibility of nano-crossbar arrays of resistive switching devices, in IEEE International Conference on Nanotechnology (2011)
23.
Zurück zum Zitat M.M. Ziegler, M.R. Stan, Design and analysis of crossbar circuits for molecular nanoelctronics, in IEEE Nano (2002) M.M. Ziegler, M.R. Stan, Design and analysis of crossbar circuits for molecular nanoelctronics, in IEEE Nano (2002)
24.
Zurück zum Zitat N.Z. Haron, S. Hamdioui, On defect oriented testing for hybrid CMOS/memristor memory. Proc. ATS (2011) N.Z. Haron, S. Hamdioui, On defect oriented testing for hybrid CMOS/memristor memory. Proc. ATS (2011)
25.
Zurück zum Zitat Y. Chen, J. Zhao, Y. Xie, 3D-NonFAR: three-dimensional non-volatile FPGA architecture using phase change memory, in 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) (2010), pp. 55–60 Y. Chen, J. Zhao, Y. Xie, 3D-NonFAR: three-dimensional non-volatile FPGA architecture using phase change memory, in 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) (2010), pp. 55–60
26.
Zurück zum Zitat S. Tanachutiwat, M. Liu, W. Wang, FPGA based on integration of CMOS and RRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst 19(11), 2023–2032 (2011) S. Tanachutiwat, M. Liu, W. Wang, FPGA based on integration of CMOS and RRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst 19(11), 2023–2032 (2011)
27.
Zurück zum Zitat Y.Y. Liauw, Z. Zhang, W. Kim, A.E. Gamal, S.S. Wong, Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2012), pp. 406–408 Y.Y. Liauw, Z. Zhang, W. Kim, A.E. Gamal, S.S. Wong, Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2012), pp. 406–408
28.
Zurück zum Zitat M. Lin, A. El Gamal, Y.-C. Lu, S. Wong, Performance benefits of monolithically stacked 3-D FPGA. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 26(2), 216–229 (2007)CrossRef M. Lin, A. El Gamal, Y.-C. Lu, S. Wong, Performance benefits of monolithically stacked 3-D FPGA. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 26(2), 216–229 (2007)CrossRef
29.
Zurück zum Zitat Y. Meng, T. Sherwood, R. Kastner, Leakage power reduction of embedded memories on FPGAs through location assignment, in 43rd ACM/IEEE Design Automation Conference (2006), pp. 612–61 Y. Meng, T. Sherwood, R. Kastner, Leakage power reduction of embedded memories on FPGAs through location assignment, in 43rd ACM/IEEE Design Automation Conference (2006), pp. 612–61
30.
Zurück zum Zitat D. Lewis et al., Architectural enhancements in stratix-III TM and stratix-IV TM, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’09) (ACM, New York, 2009), pp. 33–42 D. Lewis et al., Architectural enhancements in stratix-III TM and stratix-IV TM, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’09) (ACM, New York, 2009), pp. 33–42
31.
Zurück zum Zitat O. Turkyilmaz, S. Onkaraiah, M. Reyboz, F. Clermidy, Hraziia, C. Anghel, J.M. Portal, M. Bocquet, RRAM-based FPGA for “Normally Off, Instantly On” applications, in IEEE/ACM International Symposium on Nanoscale Architectures (2012), pp. 101–108 O. Turkyilmaz, S. Onkaraiah, M. Reyboz, F. Clermidy, Hraziia, C. Anghel, J.M. Portal, M. Bocquet, RRAM-based FPGA for “Normally Off, Instantly On” applications, in IEEE/ACM International Symposium on Nanoscale Architectures (2012), pp. 101–108
Metadaten
Titel
An Overview on Memristor-Based Non-volatile LUT of an FPGA
verfasst von
T. Nandha Kumar
Copyright-Jahr
2017
Verlag
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-4235-5_8

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