Analog Circuit Design

Implementation options for very high speed ADCs are discussed by first reviewing performance limiting mechanisms then comparing the various architectures and building blocks typically used in these converters. Results for a 5b 22GS/s ADC are presented.

Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is taking over in this former bastion of bipolar technology. We describe the issues common to all architectures: bandwidth, power, I/O, data storage, and cost. We examine these issues in detail for the time-interleaved approach as exemplified by two 8-bit ADCs operating at 4 GSa/s and 20 GSa/s, implemented in CMOS.

In this paper we want to review the development of pipelined and SAR ADCs from basic concepts to novel techniques. We will demonstrate that there are quite a lot of similarities and that there are a few major discrepancies. Based on this we draw comparisons and point out specific strengths and weaknesses of the individual architectures.

This paper presents a two-step subranging ADC architecture based on interpolation, averaging, offset compensation and pipelining techniques. Application of these techniques results in fast and power-efficient converters with an accuracy between 8b and 12b.

This paper describes how offset calibration can be used to enhance the speed-resolution performance of ADCs while maintaining low levels of power dissipation. After selecting a high-speed ADC topology, we will justify the need for offset calibration and then present a brief overview of different ADC calibration topologies, indicating their relative merits and drawbacks. We will then describe in more detail how one-time foreground calibration was used to achieve a 0.18 μm CMOS, 1.8V, 1.6GS/s, 8b folding-interpolating ADC with 7.26 ENOB at Nyquist, which only dissipates 774 mW.

In this paper a new mode of operation for Sigma-Delta Modulation (SDM) is proposed and applied to AD conversion. The proposed operation is identified as a sub-harmonic limit-cycle mode. It is shown, that in such sub-harmonic mode a more aggressive loop filter function can be applied that results in a better modulator performance. Moreover, most of the building blocks in the SDM loop operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, immunity to excessive loop delays and to DAC waveform asymmetry, and a higher tolerance to clock imperfections. The proposed SDM ADC offers an alternative to low-speed low-performance low-cost and high-speed high-performance and high-cost implementations by introducing a new trade-off between limit cycle frequency and clock frequency.

Electromagnetic emission needs to be considered in the design flow of automotive ICs. Complex ICs require on one hand early forecasts and accurate sign-offs for EMI, on the other hand their EMI modeling and simulation is very complex. Approaches and solutions are presented in this paper.

Semiconductor companies face the demand for ‘first silicon success’ to be competitive. Substrate current effects are one major cause for redesigns in junction-isolated Smart Power technologies and they put ‘first silicon success’ at risk. Substrate currents are difficult to control because they are three-dimensional in nature and are strongly layout dependent. Moreover, protection measures show counteracting effects, and minority and majority carrier effects may occur at the same time.

This chapter deals with the effect of electromagnetic interference on the operation of analog front-end like operational amplifier and switched capacitor circuits. In particular, the offset, which is generated in the input differential stage of an operational amplifier is evaluated by an analytical model and a new circuit topology immune to RFI is proposed. Furthermore, the distortion of RFI in a basic switched capacitor circuit is analyzed and a new simple model for MOS switches is derived. Such a model is employed to predict RFI-induced upset in complex SC circuits.

The design of integrated circuits for automotive applications has to meet challenging EMI requirements. In order to determine the cause of most common failures it is necessary to perform research in order to improve concept, design and layout of new or present products. In this article the concept/design analysis and results of fundamental blocks such as comparator/opamp, internal voltage supply and bandgap are presented.

This paper presents a structured methodology that, despite it is not conclusive for all cases, can support a design engineer to develop and/or debug electronic circuits for electromagnetic susceptibility (EMS). This methodology is well suited to investigate continuous time analog electronic systems, modules or circuits and does not require any special tools. The method is flexible, can be applied in many cases by simple reasoning and is customizable towards specific needs.

Modelling of ICs is mostly “just” restricted to the functional behavior of the design. Extending the modelling requirements into the EMC domain, including signal and power integrity and incorporating the application with the measurement environment requires a different approach. Fortunately, the IC in its package has only a limited number of pins/balls to the PCB connected thereto. A new approach is given which is presently under discussion and development in international standardization (IEC62433-x) by IEC SC47A/WG2, but also by other bodies like: EIA,IEEE [10, 12, 15] and/or proprietly organizations.

The governing body in the United States, the Federal Communications Commission (FCC), has issued ultra-wideband regulations, under Part15 of the Commission’s rules on April 22, 2002. Therefore, ultrawideband transmissions (intentional emissions) under certain frequency and power limitations have been permitted. The US has openly endorsed UWB based consumer products. Ultra-wideband offers significant contributions and advantages but simultaneously a number of challenges also need to be addressed. One of the key challenges is the co-design of an impulse generator and miniaturized antennas for ultra-wideband impulse radio. This has been designed and fabricated in 0.18μm CMOS technology. Measurements show the correct operation of the circuit for supply voltages of 1.8V and a power consumption of 45mW. The output pulse approximates a Gaussian monocycle having a pulse duration of about 375ps. Proper modulation of the pulse in time is confirmed [1]. In addition, to meet the stringent FCC stipulated frequency spectrum, an orthonormal [2] ladder filter with a Daubechies’ impulse response is employed. The filter is implemented using novel 2-stage gm-C cells employing negative feedback. Simulation results in CMOS 0.13μm technology show that this pulse generator requires a total current of 30mA at a 1.2V power supply. The frequency coverage of the simulated waveform is about 85% of the FCC mask.

This work describes ongoing research into system architectures, circuit design techniques, and new technologies applicable to low power wireless sensing. We will present completed proof-of-concept research as well as propose ideas for future architectures. It is shown that MEMS-based transceiver blocks in combination with a dedicated carrier sense receiver can substantially reduce the communications energy of a sensor network. Additionally, novel methods for power regulation and modular packaging will be introduced.

This paper studies the different power-performance trade-offs at architectural and block level to come to the most energy-efficient UWB system for operation in the 0-960MHz frequency band. This is achieved by designing for the lowest energy per useful received bit. Different receiver architectures are explored and compared against each other. After the selection of the most optimal architecture, the trade-offs inside the different analog building blocks of this receiver are studied. Our results show that the most energy-efficient solution makes use of a complex analog correlation UWB receiver, with an LNA with a P_in,1dBc back-off of -5dB, 3-bit ADC’s and a 500MHz QVCO. The requirements for the ADC offset, QVCO phase noise and mixer linearity are rather relaxed, which enables a low-power implementation.

The number of available electronic implantable devices is increasing every year. The complexity and functionality of these devices is also increasing at a significant rate. Communications with these complex devices for physician adjustment and to collect data is becoming increasingly important to provide the maximum patient comfort and the most effective treatment for medical conditions. A Communications band has been allocated in both North American and Europe specifically for communications with implanted devices. This paper reviews some of the unique requirements for an implanted wireless transceiver, regulatory requirements of the Medical Implantable Communication Service (MICS) band, provides a description of a product competing in this arena and a unique crystal startup circuit that can significantly reduce power consumption in power critical implant applications.

Autonomy and size are the most important challenges faced when designing radios for distributed wireless sensor networks (WSN). Reducing power consumption requires optimization across all the layers of the communication stack. The WSN platform developed at CSEM therefore uses a co-design approach that combines WiseMAC, a low-power media access control protocol, with the WiseNET SoC, a complex system-on-chip sensor node to exploit the intimate relationship between the MAC-layer and the radio transceiver parameters. This paper reviews the design and realization of the WiseNET SoC featuring a low-power 1V short-range UHF radio transceiver implemented on a 0.18μm standard digital CMOS process. The WiseNET radio consumes only 2.3mW in receive mode with a sensitivity smaller than -108-dBm at a BER of 10^-3 for 25kb/s FSK in the 433MHz ISM band. The design, simulation and validation of the WiseMAC protocol are also detailed in the context of the deployment of a small ad-hoc network experiment at CSEM, demonstrating that the consumption of the WiseNET solution is more than an order of magnitude lower than a comparable Zigbee-based solution.

This paper examines system and circuit design techniques for a micro-Watt node operating at a power level low enough to enable the use of an energy scavenging source. Despite several architectures have been investigated in order to reduce the overall system power consumption, none of them is able to guarantee robustness of the link and ultra-low power consumption at the same time. A survey of the most advanced architectures meant for ultra-low power transceivers is described. Advantages and drawbacks of all these systems are discussed and the reasons for an architecture based on Frequency-Hopping (FH) Spread-Spectrum (SS) are discussed. Finally a novel FH synthesizer based on a digital pre-distortion architecture is proposed in order to reduce the power consumption of the hopping synthesizer. The FH architecture together with a frequency offset robust demodulation technique allows a reduction by a factor 8 of the power consumption compared to the state-of-the-art synthesizers. Furthermore, a single RF block front-end is obtained combining the VCO and the PA. The novel RF front-end can be directly coupled to the antenna through a balun and the system is able to deliver -18 dBm output power on a 50 Ω load at 1 mA current consumption (2 V power supply). To prove the new synthesizer principle a communication link in the 902-928 MHz ISM band has been set-up. The receiver, mainly software with a flexible RF frontend, adopted a ST-DFT demodulation algorithm and achieved a BER smaller than 1.1% at -25 dBm output power, with TX and RX antennas placed at 8 meters distance in a NLOS condition and in a common office environment.