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Über dieses Buch

Analog Circuit Design contains the contribution of 18 tutorials of the 19th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of:

Robust Design,

chaired by Herman Casier, ConsultantSigma Delta Converters,

chaired by Prof. Michiel Steyaert, Catholic University LeuvenRFID,

chaired by Prof. Arthur van Roermund, Eindhoven University of Technology

Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design course.



Part I

Modeling and Design for Reliability of Analog Integrated Circuits in Nanometer CMOS Technologies

Advanced scaling of CMOS technology in the nanometer range allows to design highly integrated mixed-signal systems, but also poses many challenges due to increased variability and reliability problems. Both have to be addressed by the designer, at IC design time or at IC run time. Design tools for the efficient analysis of reliability problems in analog circuits are described. This allows identifying potential ageing problems in circuits. In addition, run-time circuit adaptation/reconfiguration techniques are presented that allow a circuit to self-recover from degradation failures. These techniques are fully compliant with the trend towards digitally assisted analog circuits.
Georges Gielen, Elie Maricau, Pieter De Wit

Modeling and Simulation of Statistical Variability in Nanometer CMOS Technologies

In this chapter we introduce different sources of statistical variability and their impact on the characteristics of nanoscale transistors. We present accurate statistical compact model strategies suitable for statistical analogue design. We also study the impact of statistical variability on the design of SRAM cell and possible counter measures that can reduce the impact of the variability and can improve the SRAM yield.
A. Asenov, B. Cheng

Advanced Physical Design in Nanoscale Analog CMOS

As the EDA industry strives to keep pace with advancements in process technology, CMOS IC verification tools are identifying a wider range of circuit and physical design deficiencies. While the EDA tools have shown considerable progress, problems found in post-layout verification can result in significant additional redesign and re-layout time. Circuit and layout redesign effort wastes the semiconductor industries most valuable commodity, time to market. One objective of this paper is to identify many factors adversely affecting successful nanoscale analog physical design. However, the primary objective is to propose methods for mitigating or overcoming physical design problems, so that the future of deep-nanoscale analog CMOS looks a bit brighter. One key to the basic approach is to propose certain restrictions on device design at the initial circuit design stage and another is to achieve increased regularity in physical design at circuit layout.
Lanny L. Lewyn

Robust Design for High Temperature and High Voltage Applications

The automotive industry developments in the electrification of power train systems (i.e. HEVs and EVs), chassis systems (i.e. X-by wire systems) and auxiliaries (e.g. HVAC) have created a rapidly growing demand of advanced high temperature robust and reliable power electronics systems. This will require further efforts both in nanoelectronics semiconductor basic technologies and in system integration: power electronic system coming from industrial segments, need to be qualified against automotive requirements in term of reliability, robustness, safety and dependability. The paper gives an overview of the semiconductor technologies and integrated electronics for electrical power systems in particular for electric vehicles (EVs) and hybrid electric vehicles (HEVs). In addition it will discuss the mapping of the semiconductor technologies to the module electronics requirements aiming to the highest levels of reliability (target zero defects).
Ovidiu Vermesan, Edgard Laes, Marco Ottella, Mamun Jamal, Jan Kubik, Kafil M. Razeeb, Reiner John, Harald Gall, Massimo Abrate, Nicolas Cordero, Jan Vcelak

Radiation Effects and Hardening by Design in CMOS Technologies

The main radiation effects threatening the reliable functionality of CMOS Integrated Circuits (ICs) are presented evidencing how they scale in modern deep submicron technologies. Hardening By Design (HBD) techniques can be applied in commercial-grade CMOS leading to robust ICs capable of satisfying the requirements of space, avionics, nuclear and High Energy Physics (HEP) applications. These techniques are described and their respective advantages and inconveniences are discussed.
Federico Faccio

EMC Robust Design for Smart Power High Side Switches

The continued increase of electric and electronic systems in modern cars leads to growing electromagnetic noise which increases the risk of interference to the functional integrity of the system. This places greater demands to predict integrated circuit (IC) electromagnetic immunity in the early design phase. This paper describes an approach to early define the immunity of smart power automotive high side switches by using Direct Power Injection (DPI) simulations. A methodology will be presented to transform IC robustness requirements from a DPI level into a supply noise level, as a result of pin to pin impedance design.
Paolo Del Croce, Bernd Deutschmann

Part II: Sigma Delta Converters

Noise-Coupled Delta-Sigma ADCS

This chapter describes wideband discrete-time DS ADCs with high linearity. Noise coupling is introduced in a modulator (self coupling) or between two split modulators (cross coupling) to get an improved noise shaping performance. Time-interleaving further enhances the noise shaping of the cross-coupled split modulators. Several prototype design examples are provided to demonstrate the effectiveness of the proposed technique.
Kyehyung Lee, Gabor C. Temes

Very Low OSR Sigma-Delta Converters

This chapter investigates ΣΔ modulators and incremental A/D converters at low oversampling ratios. Both architectures have advantages at reduced OSRs; incremental A/D converters are able to achieve higher SQNR than ΣΔ modulators at oversampling ratios below 8, and ΣΔ modulators can attain better thermal noise performance than pipeline A/D converters at low OSRs. Both architectures are analyzed and a sample 8th-order cascaded architecture is demonstrated for both topologies.
Trevor C. Caldwell

Comparator-Based Switched-Capacitor Delta-Sigma A/D Converters

In comparator-based switched-capacitor circuits, OTAs are replaced by comparators and current sources. Instead of an OTA forcing a virtual ground condition, a comparator steers current sources until it detects a virtual ground. Different possibilities to use this principle in a ΔΣ A/D converter are evaluated. A pseudo-differential implementation with preset minimizes the requirements for the comparator and the current source. Due to the operation of the circuit, feed-back noise-shaping filters with half delay integrators are preferable. An implementation of a comparator-based switched-capacitor ΔΣ A/D converter in a 1 V, 90 nm CMOS technology demonstrates the feasibility.
Koen Cornelissens, Michiel Steyaert

VCO-Based Wideband Continuous-Time Sigma-Delta Analog-to-Digital Converters

This chapter examines the use of VCO-based quantization within continuous-time, Sigma-Delta ADC circuits. We consider the VCO-based quantizer as an efficient combination of a voltage-to-time converter and a time-to-digital converter, and discuss the advantages it offers in achieving improved quantization noise performance in the ADC. However, the common approach of using frequency as the output of the VCO-based quantizer presents a bottleneck to achieving high SNDR in the ADC due to Kv nonlinearity. We show that using phase as the key output variable removes this nonlinearity barrier. Measured results confirm that 78 dB SNDR performance is achievable with 20 MHz bandwidth while achieving a 330 fJ/conversion step efficiency.
Michael H. Perrott

Wideband Continuous-Time Multi-Bit Delta-Sigma ADCs

This chapter deals with the design of DS modulators for wireless applications. Two case studies are presented to discuss general design issues and to give insights into the possibilities that exist for solving contemporary challenges with time-domain processing techniques. The first architecture employs a time-to-digital converter based on pulse-width. Its time-based single-level DAC achieves linear multi-bit feedback, leading to the DS modulator’s dynamic range of 68 dB. The second architecture employs a 7-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and DAC. Fabricated in a 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW, and occupies a die area of 2.6 mm2. This modulator has a measured SFDR of 78 dB and in-band IM3 under −72 dB at −2dBFS.
J. Silva-Martinez, C.-Y. Lu, M. Onabajo, F. Silva-Rivas, V. Dhanasekaran, M. Gambhir


In this chapter the fundamental theory and advanced solution for oversampled DACs will be presented. Oversampled DACs are the only solution for audio codecs, which require DR in excess of 16 bit, THD in excess of 80 dB. For this reason audio cases are presented and studied in details. Finally the recent CMOS scaled technologies perform higher speed and then the concepts of oversampled DACs have been recently applied to larger bandwidth devices, indicating a future interesting development of oversampled DACs.
Andrea Baschirotto, Vittorio Colonna, Gabriele Gandolfi


RFID, a Technology Ready for Industry Deployment

RFID is not a new technology. It has been around since more than 50 years. However, it is only in the early two thousands that RFID became popular across a large range of businesses. Many have already implemented RFID for some specific business processes. Many more are contemplating the opportunities offered by this technology. This article starts with an historical overview. It follows with an analysis of the RFID market landscape. RFID standards are presented and discussed next. A summary of the EU partly funded BRIDGE project that performed applied research, pilot implementations in several sectors and delivered a comprehensive set of demonstration and training material is provided. The Privacy concerns triggered by the present and future applications of RFID are presented together with an overview of the regulations related to the frequencies allocated to RFID. The potential economic impact of RFID is very large. Economic impacts resulting from the usage of RFID could be on an order of magnitude higher. These come in the form of cost reductions/productivity growth and, increasingly, in the form of new products and services.
Henri Barthel

The World’s Smallest RFID Chip Technology

Ultra-small radio frequency identification (RFID) chip and antenna technology are described. The key technologies used in this ultra-small chip to reduce chip size and cost are embedded antenna, electron beam (EB) memory, double-surface electrode and silicon on insulator (SOI).
Mitsuo Usami

RF and Low Power Analog Design for RFID

A passive RFID tag consists of an antenna and IC operating without a battery. The DC power required to operate the IC is generated by converting the incoming RF field to a DC supply using a rectifier. The minimum DC power available from the rectifier is on the order of a few micro-watts, and this is the power available to operate the tag, comprised of various sub-systems. Each sub-system is typically allocated only hundreds of nano-watts of DC power to operate. The basic functional analog sub-systems of the IC include rectifier, RF and DC power management, data receiver, backscatter modulator, non-volatile memory controller, and additional supporting sub-circuits. This paper addresses several aspects of the design of RF and Analog Front End circuits for RFID.
Raymond Barnett

A Dual Frequency Band Comprehensive RFID TAG

Passive RFID applications are in place in several ISM frequency bands. The three most important bands are: LF (100–135 kHz), HF (13.56 MHz) and UHF (860–960 MHz). Which band is selected depends on the application, on the national radio regulations, on the established RFID infrastructure in this segment or on costs. This work proposes a passive RFID analog front end which operates at two RFID frequency bands. For contactless communication the EPC Gen2 UHF and the EPC HF standard have been implemented. For this purpose a novel single port power generation unit which comprises one wideband rectifier and two low voltage DC/DC converters has been designed. A low power and low voltage local oscillator unit and a new concept for contactless communication including ultra low power circuits for modulation and demodulation are presented. The test chip has been manufactured in a low cost 120 nm Infineon process with EEPROM technology.
Albert Missoni, Günter Hofer, Wolfgang Pribyl

Printed Electronics—First Circuits, Products, and Roadmap

Printed electronics is a new kind of platform technology enabling many applications of low-cost, thin and flexible, as well as high-volume electronics. This article gives a brief introduction into the field. The performance potential of printed circuits with focus on printed RFID is discussed by examining the performance figures of a printed ring oscillator, a transponder chip with Manchester-encoded 4-bit IDs and results on a field trial with ID-less RF transponders. The “OE-A Roadmap for Organic and Printed Electronics” is outlined with focus on RFID. It defines nine major application fields of organic and printed electronics as well as the anticipated short-term to long-term progress of these fields.
Jürgen Krumm, Wolfgang Clemens

Towards EPC-Compatible Organic RFID Tags

In this chapter, fully integrated organic RFID tags are demonstrated. These tags are inductively-coupled at a base frequency of 13.56 MHz and can be read out at distances up to 10 cm, which is the expected readout distance for proximity readers. We also demonstrate next generation transponder chips, fabricated in a dual-gate technology. The additional gate, backgate, is used to control the threshold voltage and allows integration into more robust unipolar, dual-VT transponder chips. Finally, we realized an 8-bit transponder chip having data rates that are EPC-compatible. This has been achieved in our thin-film transistor technology by introducing a high-k Al2O3 gate dielectric, by scaling the channel lengths down to 2 mm and by reducing the overlap capacitance of the parasitic source-gate and drain-gate capacitors.
Kris Myny, Soeren Steudel, Peter Vicca, Steve Smout, Monique J. Beenhakkers, Nick A.J.M. van Aerle, François Furthner, Bas van der Putten, Ashutosh K. Tripathi, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans
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