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Über dieses Buch

Integrated circuits are fundamental electronic components in biomedical, automotive and many other technical systems. A small, yet crucial part of a chip consists of analog circuitry. This part is still in large part designed by hand and therefore represents not only a bottleneck in the design flow, but also a permanent source of design errors responsible for re-designs, costly in terms of wasted test chips and in terms of lost time-to-market. Layout design is the step of the analog design flow with the least support by commercially available, computer-aided design tools. This book provides a survey of promising new approaches to automated, analog layout design, which have been described recently and are rapidly being adopted in industry.





Chapter 1. Device-Level Topological Placement with Symmetry Constraints

The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations (called flat representations of the layout), where the cells are moved in the chip plane by a stochastic optimizer – like simulated annealing or a genetic algorithm. This chapter discusses the possible use in analog placement problems with symmetry constraints of topological representations of the layout, encoding systems that are not restricted to slicing floorplan topologies. First, the chapter gives an overview of several data structures that may be used in the evaluation of various topological representations of the layout – therefore, in building the placement from the layout encoding. Afterwards, the chapter presents a subset of sequence-pairs – called “symmetric-feasible” – that allows to take into account the presence of an arbitrary number of symmetry groups of devices during the exploration of the solution space. Alternatively, the possible use of tree representations instead of “symmetric-feasible” sequence-pairs is also discussed. The computation times exhibited by the topological approaches are significantly better than those of the placement algorithms using the traditional exploration strategy based on flat representations, while preserving a similar quality of the placement solutions.
Florin Balasa

Chapter 2. Hierarchical Placement with Layout Constraints

In analog layout design, devices are required to be placed with matching, symmetry, and proximity constraints to reduce parasitic coupling effects and improve circuit performance. In addition to these basic placement constraints, there exist hierarchical symmetry and hierarchical proximity constraints due to circuit and layout design hierarchies. This chapter first introduces the hierarchical constraints induced by circuit and layout design hierarchies, and then presents a hierarchical placement approach to better consider these hierarchical constraints and effectively reduce the search space.
Mark Po-Hung Lin, Yao-Wen Chang

Chapter 3. Deterministic Analog Placement by Enhanced Shape Functions

For analog integrated circuits, generating a layout represents the bottleneck in the design flow. To automate the layout step, it is necessary to create placements with respect to various constraints automatically. Since the constraints can be numerous, an automatic generation of the layout constraints is crucial as well. In this chapter, a comprehensive and deterministic methodology for analog layout design automation is presented. An approach to automatically generate constraints for analog circuits is described. It recognizes building blocks, e.g., current mirrors, and symmetry conditions in the circuit and, with prioritized rules, generates constraints and hierarchy information. Then, a placement algorithm, called “Plantage”, is presented, which is capable to handle all relevant constraints. It uses the hierarchy information of the previous step to guide an enumeration process. Plantage calculates a Pareto front of placements with respect to different aspect ratios. The results show high quality in terms of area and postlayout circuit performance.
Martin Strasser, Michael Eick, Helmut Graeb, Ulf Schlichtmann



Chapter 4. Routing Analog Circuits

This chapter presents a review of routers for analog circuits, some practical issues for analog routing, and a template-based routing strategy. Basic algorithms and methods used for routing are discussed first, starting from the maze router and continuing towards more sophisticated routing algorithms. Then, data representations commonly used for routing are described in some detail. Analog design specific routing issues and methods are then discussed. Various routing strategies from the literature and developed by the authors are presented in some detail. Specialized routers for two analog applications, namely RF design and analog arrays, are also presented. Manufacturing and yield issues for routing are discussed briefly before conclusions and a discussion of various open problems in routing of analog integrated circuits
Günhan Dündar, Ahmet Unutulmaz

Layout in the Design Flow


Chapter 5. Analog Layout Retargeting

This chapter focuses on analog layout process retargeting. Unlike automatic placement and routing tools, retargeting starts with an input layout in 6 a given process. The main target is to conserve most of the layout physical intelli- gence while migrating it to another given technology. This is usually achieved by adapting existing layout compaction techniques borrowed from the digital world. Historically, layout compaction used to rely on fast constraint-graph operations. More recently, linear programming has been introduced to support hierarchy in ad- dition to complex analog constraints. This chapter introduces a novel graph-based simplex algorithm that combines the efficiency of graph-based methods together with the generality of linear programming ones. It also allows symmetry, hierar-chy, and cell replacement support to be integrated seamlessly without any artificial modification of the algorithm. For simple layout constraints, the algorithm com- plexity tends to be as linear as graph-based techniques, while for the most complex constraints and objective function it tends to that of the simplex method.
Hazem Said, Mohamed Dessouky, Reem El-Adawi, Hazem Abbas, Hussein Shahein

Chapter 6. Closing the Gap Between Electrical and Physical Design: The Layout-Aware Solution

Iterations between separate phases in any procedural design process, usually a by-product of unexpected (or, simply, very complex to consider) adverse effects, clearly play against any time-to-market requirements. In analog integrated circuit (IC) design, going back and forth between electrical and physical synthe- sis to counterbalance layout-induced performance degradations needs to be thus avoided as much as possible. One possible solution involves the integration of the 1 traditionally separated electrical and physical synthesis phases, by including layout- induced effects, in the form of layout parasitics, right into the electrical synthesis phase, in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of the occu- pied area or fulfillment of certain layout aspect ratio, among others), whose effects on the resulting parasitics are not usually considered during electrical synthesis. In this chapter, a layout-aware solution that tackles both geometric and parasitic-aware electrical synthesis is proposed. This technique uses a combination of simulation- based optimization, procedural layout generation, exhaustive geometric evaluation algorithms, and several mechanisms for parasitic estimation. Thanks to the nature of this combination, the solution benefits from, and also fosters, reuse of analog intellectual property (IP) blocks. Several detailed design examples are provided.
Rafael Castro-Lόpez, Elisenda Roca, Francisco V. Fernández

Chapter 7. Constraint-Driven Design Methodology: A Path to Analog Design Automation

Physical design for analog ICs has not been automated to the same degree as digital IC design, but such automation can significantly improve the productivity of circuit engineers. Analog design remains difficult to formalize due to a large amount of expert knowledge involved, such as sophisticated constraints that are specified manually and satisfied through manual layout. We therefore propose a constraint-driven design methodology – a suite of algorithms and methodologies to capture key rules governing analog layouts and to produce layouts that satisfy these rules. In this chapter, we identify major challenges in analog physical design, and relate them to constraints.We introduce techniques for constraint representation and highlight the essential components of a constraint-driven design methodology. Finally, we explain how constraint-driven design impacts a typical analog design flow, layout algorithms, and the overall physical design methodology.
Göran Jerke, Jens Lienig, Jan B. Freuer


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