Analog/RF and DC Performance Enhancement of a Pocket-Doped Junction-Less TFET for Low Power Application

The Junction-less tunnel field-effect transistor (JLTFET) is a captivating device due to its excellent electrical properties and less variability in comparison to MOSFET at the nanometer regime. In this regard, we investigate a silicon-based pocket doped JLTFET in which an InAs pocket is inserted across the source-channel junction to enhance tunneling probability. In this respect, we have considered analog/RF and DC Figure of merit analysis for the conventional and pocket doped JLTFET (PD- JLTFET) in terms of an electric field, transfer characteristics, transconductance, parasitic capacitances, cut-off frequency, gain-bandwidth product, and maximum oscillation frequency. Additionally, we have examined the effect of spacer length variation across the junction between source and channel. The ATLAS device simulator is used for the simulations of the conventional JLTFET and PD-JLTFET. The proposed PD-JLTFET has shown a higher I_ON/I_OFF ratio (~10¹³) and improved sub-threshold swing (~9.08 mV/decade). The notable characteristics demonstrated by PD-JLTFET make it an optimum device for low power and high switching application.