FinFET technology is used in leading high-performance/power-efficient electronic products. This technology has proven its efficiency after 22nm technology nodes. However, FinFET technology has new manufacturing and design complexities. Thus, it is required to study the behavior of defects in FinFET-based SRAM memories and develop new test strategies for those not covered by conventional test strategies based on CMOS fault modeling. This paper study open-gate defects affecting only one of the parallel fins in the driver transistors of the memory cell. These opens do not cause a functional fault but reduce the Static Noise Margin (SNM) of the memory cells. Moreover, they may fail under certain operating conditions and may constitute a long-term reliability issue. The behavior of these defects is studied for the hold, read and write operations using realistic defect models. By using a short write time test, the detection of these defects is investigated. The effectiveness of the short write time test method at nominal parameters and under process variations is evaluated. The detection probability of these defects can be further enhanced using a higher power supply voltage.
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