Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices

In present scenario, the portable wireless devices like mobile phones are used by almost every human being for communication purpose. Mobile devices are equipped with a processing element that is responsible for performing all the controlling and computational tasks. Most of the computational tasks inside the processing element are performed by ALU circuit. ALU is considered as the computational engine and responsible for high power consumption. Previously, microprocessors and microcontrollers were the choice of designers but nowadays the horizon has been shifted to FPGAs and SOCs as a processing element in mobile devices. Obviously, FPGAs have numerous advantages over processors and the growing need of applications compels the designers to use FPGAs for fast processing. Although FPGAs fulfils the requirement of designers but they suffer from the disadvantage of high power consumption due to their complex circuitry. The demand of high performance and low power devices creates a bottleneck in front of designers specifically for battery operated portable wireless devices. So, this paper presents some power minimization techniques that can be applied on communication centric designs targeted to FPGAs. There are different techniques given in the literature but most of them are applied at device level only. This paper gives an insight to minimize the power at architectural level of design hierarchy using XPower Analyzer as a CAD tool. The proposed techniques are applied on arithmetic and logical unit circuit for analysis purpose, as ALU is the heart of processing elements used in portable wireless devices. The circuit has been verified and realized on XILINX ISE directed to Spartan 3E XC3S250E FPGA. The analysis illustrates significant improvement in the power consumption.