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2015 | OriginalPaper | Buchkapitel

6. Analyzing Timing Variations

verfasst von : Mehdi Dehbashi, Görschwin Fey

Erschienen in: Debug Automation from Pre-Silicon to Post-Silicon

Verlag: Springer International Publishing

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Abstract

Variability is recognized to be a major challenge in analyzing the circuits as IC technology continues to scale down. In this case, delay deviations are imposed by process variations such as uncertainty in the parameters of fabricated devices and interconnects, and by environmental variations such as temperature and voltage [BCSS08, APP10, SGT+08].

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Fußnoten
1
At the end of Sect. 6.2.3, we discuss how more complex timing models can be handled by our approach.
 
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[KNKB08]
Zurück zum Zitat Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, and Pouria Bastani. Case study on speed failure causes in a microprocessor. IEEE Design & Test of Computers, 25(3):224–230, 2008.CrossRef Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, and Pouria Bastani. Case study on speed failure causes in a microprocessor. IEEE Design & Test of Computers, 25(3):224–230, 2008.CrossRef
[Lar92]
Zurück zum Zitat Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(1): 4–15, 1992.CrossRef Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(1): 4–15, 1992.CrossRef
[LCB+10]
Zurück zum Zitat Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, and Subhasish Mitra. ERSA: Error resilient system architecture for probabilistic applications. In Proceedings of Design, Automation and Test in Europe, pages 1560–1565, 2010. Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, and Subhasish Mitra. ERSA: Error resilient system architecture for probabilistic applications. In Proceedings of Design, Automation and Test in Europe, pages 1560–1565, 2010.
[LDX12]
Zurück zum Zitat Min Li, Azadeh Davoodi, and Lin Xie. Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. In Proceedings of Design, Automation and Test in Europe, pages 1591–1596, 2012. Min Li, Azadeh Davoodi, and Lin Xie. Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. In Proceedings of Design, Automation and Test in Europe, pages 1591–1596, 2012.
[LEN+11]
Zurück zum Zitat Avinash Lingamneni, Christian Enz, Jean-Luc Nagel, Krishna Palem, and Christian Piguet. Energy parsimonious circuit design through probabilistic pruning. In Proceedings of Design, Automation and Test in Europe, pages 764–769, 2011. Avinash Lingamneni, Christian Enz, Jean-Luc Nagel, Krishna Palem, and Christian Piguet. Energy parsimonious circuit design through probabilistic pruning. In Proceedings of Design, Automation and Test in Europe, pages 764–769, 2011.
[LGD12]
Zurück zum Zitat Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(8):1249–1262, 2012.CrossRef Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(8):1249–1262, 2012.CrossRef
[LLC07]
Zurück zum Zitat Yung-Chieh Lin, Feng Lu, and Kwang-Ting Cheng. Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(5):932–942, 2007.CrossRef Yung-Chieh Lin, Feng Lu, and Kwang-Ting Cheng. Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(5):932–942, 2007.CrossRef
[LMF11]
Zurück zum Zitat Yeonbok Lee, Takeshi Matsumoto, and Masahiro Fujita. On-chip dynamic signal sequence slicing for efficient post-silicon debugging. In Proceedings of the ASP Design Automation Conference, pages 719–724, 2011. Yeonbok Lee, Takeshi Matsumoto, and Masahiro Fujita. On-chip dynamic signal sequence slicing for efficient post-silicon debugging. In Proceedings of the ASP Design Automation Conference, pages 719–724, 2011.
[LRS89]
Zurück zum Zitat Wing-Ning Li, Sudhakar M Reddy, and Sartaj K Sahni. On path selection in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56–63, 1989. Wing-Ning Li, Sudhakar M Reddy, and Sartaj K Sahni. On path selection in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56–63, 1989.
[LS80]
Zurück zum Zitat Jean Davies Lesser and John J. Shedletsky. An experimental delay test generator for LSI logic. IEEE Transactions on Computers, 100(3):235–248, 1980. Jean Davies Lesser and John J. Shedletsky. An experimental delay test generator for LSI logic. IEEE Transactions on Computers, 100(3):235–248, 1980.
[LV05]
Zurück zum Zitat Jiang Brandon Liu and Andreas Veneris. Incremental fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2): 240–251, 2005. Jiang Brandon Liu and Andreas Veneris. Incremental fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2): 240–251, 2005.
[LWPM05]
Zurück zum Zitat Leonard Lee, Li-C. Wang, Praveen Parvathala, and T. M. Mak. On silicon-based speed path identification. In Proceedings of the VLSI Test Symposium, pages 35–41, 2005. Leonard Lee, Li-C. Wang, Praveen Parvathala, and T. M. Mak. On silicon-based speed path identification. In Proceedings of the VLSI Test Symposium, pages 35–41, 2005.
[LX10]
Zurück zum Zitat Xiao Liu and Qiang Xu. On signal tracing for debugging speedpath-related electrical errors in post-silicon validation. In Proceedings of the IEEE Asian Test Symposium, pages 243–248, 2010. Xiao Liu and Qiang Xu. On signal tracing for debugging speedpath-related electrical errors in post-silicon validation. In Proceedings of the IEEE Asian Test Symposium, pages 243–248, 2010.
[Mal87]
Zurück zum Zitat Wojciech Maly. Realistic fault modeling for VLSI testing. In Proceedings of the Design Automation Conference, pages 173–180. ACM, 1987. Wojciech Maly. Realistic fault modeling for VLSI testing. In Proceedings of the Design Automation Conference, pages 173–180. ACM, 1987.
[MB91]
Zurück zum Zitat Patrick C McGeer and Robert K Brayton. Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Kluwer Academic Publishers, 1991. Patrick C McGeer and Robert K Brayton. Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Kluwer Academic Publishers, 1991.
[MCRR11]
Zurück zum Zitat Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, and Kaushik Roy. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of Design, Automation and Test in Europe, pages 950–955, 2011. Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, and Kaushik Roy. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of Design, Automation and Test in Europe, pages 950–955, 2011.
[MJR86]
Zurück zum Zitat Yashwant K Malaiya, AP Jayasumana, and R Rajsuman. A detailed examination of bridging faults. In International Conference on Computer Design, pages 78–81, 1986. Yashwant K Malaiya, AP Jayasumana, and R Rajsuman. A detailed examination of bridging faults. In International Conference on Computer Design, pages 78–81, 1986.
[MMSTR09]
Zurück zum Zitat Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, and Janusz Rajski. Timing-aware multiple-delay-fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):245–258, 2009.CrossRef Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, and Janusz Rajski. Timing-aware multiple-delay-fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):245–258, 2009.CrossRef
[MS95]
Zurück zum Zitat Joao Marques-Silva. Search algorithms for satisfiability problems in combinational switching circuits. PhD thesis, University of Michigan, 1995. Joao Marques-Silva. Search algorithms for satisfiability problems in combinational switching circuits. PhD thesis, University of Michigan, 1995.
[MS07]
Zurück zum Zitat Wolfgang Mayer and Markus Stumptner. Model-based debugging–state of the art and future challenges. Electronic Notes in Theoretical Computer Science, 174(4): 61–82, 2007.CrossRef Wolfgang Mayer and Markus Stumptner. Model-based debugging–state of the art and future challenges. Electronic Notes in Theoretical Computer Science, 174(4): 61–82, 2007.CrossRef
[MVL09]
Zurück zum Zitat Richard McLaughlin, Srikanth Venkataraman, and Carlston Lim. Automated debug of speed path failures using functional tests. In Proceedings of the VLSI Test Symposium, pages 91–96, 2009. Richard McLaughlin, Srikanth Venkataraman, and Carlston Lim. Automated debug of speed path failures using functional tests. In Proceedings of the VLSI Test Symposium, pages 91–96, 2009.
[MVS+07]
Zurück zum Zitat Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Farid N Najm, and Magdy S Abadir. Maximum circuit activity estimation using pseudo-boolean satisfiability. In Proceedings of Design, Automation and Test in Europe, pages 1538–1543, 2007. Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Farid N Najm, and Magdy S Abadir. Maximum circuit activity estimation using pseudo-boolean satisfiability. In Proceedings of Design, Automation and Test in Europe, pages 1538–1543, 2007.
[OHN09]
Zurück zum Zitat Sari Onaissi, Khaled R. Heloue, and Farid N. Najm. PSTA-based branch and bound approach to the silicon speedpath isolation problem. In Proceedings of the International Conference on Computer-Aided Design, pages 217–224, 2009. Sari Onaissi, Khaled R. Heloue, and Farid N. Najm. PSTA-based branch and bound approach to the silicon speedpath isolation problem. In Proceedings of the International Conference on Computer-Aided Design, pages 217–224, 2009.
[PGI+05]
Zurück zum Zitat Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, and Giovanni De Micheli. Design, synthesis, and test of networks on chips. IEEE Design & Test of Computers, 22(5):404–413, 2005. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, and Giovanni De Micheli. Design, synthesis, and test of networks on chips. IEEE Design & Test of Computers, 22(5):404–413, 2005.
[PGSR10]
Zurück zum Zitat Mihalis Psarakis, Dimitris Gizopoulos, Edgar Sánchez, and Matteo Sonza Reorda. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 27(3):4–19, 2010. Mihalis Psarakis, Dimitris Gizopoulos, Edgar Sánchez, and Matteo Sonza Reorda. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 27(3):4–19, 2010.
[PHM09]
Zurück zum Zitat Sung-Boem Park, Ted Hong, and Subhasish Mitra. Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10): 1545–1558, 2009.CrossRef Sung-Boem Park, Ted Hong, and Subhasish Mitra. Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10): 1545–1558, 2009.CrossRef
[QW03]
Zurück zum Zitat Wangqi Qiu and D. M. H. Walker. An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit. In Proceedings of the International Test Conference, pages 592–601, 2003. Wangqi Qiu and D. M. H. Walker. An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit. In Proceedings of the International Test Conference, pages 592–601, 2003.
[Rei87]
[RGU09]
Zurück zum Zitat Jaan Raik, Vineeth Govind, and Raimund Ubar. Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Computers & Digital Techniques, 3(5):476–486, 2009.CrossRef Jaan Raik, Vineeth Govind, and Raimund Ubar. Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Computers & Digital Techniques, 3(5):476–486, 2009.CrossRef
[RS04]
Zurück zum Zitat Kavita Ravi and Fabio Somenzi. Minimal assignments for bounded model checking. In Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of LNCS, pages 31–45, 2004. Kavita Ravi and Fabio Somenzi. Minimal assignments for bounded model checking. In Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of LNCS, pages 31–45, 2004.
[SAKJ10]
Zurück zum Zitat Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, and Douglas L. Jones. Stochastic computation. In Proceedings of the Design Automation Conference, pages 859–864, 2010. Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, and Douglas L. Jones. Stochastic computation. In Proceedings of the Design Automation Conference, pages 859–864, 2010.
[SCPB12]
Zurück zum Zitat Matthias Sauer, Alexander Czutro, Ilia Polian, and Bernd Becker. Small-delay-fault ATPG with waveform accuracy. In Proceedings of the International Conference on Computer-Aided Design, pages 30–36, 2012. Matthias Sauer, Alexander Czutro, Ilia Polian, and Bernd Becker. Small-delay-fault ATPG with waveform accuracy. In Proceedings of the International Conference on Computer-Aided Design, pages 30–36, 2012.
[SD10]
Zurück zum Zitat André Sülflow and Rolf Drechsler. Automatic fault localization for programmable logic controllers. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 247–256, 2010. André Sülflow and Rolf Drechsler. Automatic fault localization for programmable logic controllers. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 247–256, 2010.
[SFB+09]
Zurück zum Zitat André Sülflow, Goerschwin Fey, Cécile Braunstein, Ulrich Kühne, and Rolf Drechsler. Increasing the accuracy of SAT-based debugging. In Proceedings of Design, Automation and Test in Europe, pages 1326–1332, 2009. André Sülflow, Goerschwin Fey, Cécile Braunstein, Ulrich Kühne, and Rolf Drechsler. Increasing the accuracy of SAT-based debugging. In Proceedings of Design, Automation and Test in Europe, pages 1326–1332, 2009.
[SFBD08]
Zurück zum Zitat André Sülflow, Goerschwin Fey, Roderick Bloem, and Rolf Drechsler. Using unsatisfiable cores to debug multiple design errors. In Great Lakes Symposium VLSI, pages 77–82, 2008. André Sülflow, Goerschwin Fey, Roderick Bloem, and Rolf Drechsler. Using unsatisfiable cores to debug multiple design errors. In Great Lakes Symposium VLSI, pages 77–82, 2008.
[SFD10]
Zurück zum Zitat André Sülflow, Goerschwin Fey, and Rolf Drechsler. Using QBF to increase accuracy of SAT-based debugging. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 641–644, 2010. André Sülflow, Goerschwin Fey, and Rolf Drechsler. Using QBF to increase accuracy of SAT-based debugging. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 641–644, 2010.
[SG10]
Zurück zum Zitat Doochul Shin and Sandeep K. Gupta. Approximate logic synthesis for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 957–960, 2010. Doochul Shin and Sandeep K. Gupta. Approximate logic synthesis for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 957–960, 2010.
[SG11]
Zurück zum Zitat Doochul Shin and Sandeep K. Gupta. A new circuit simplification method for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 1566–1571, 2011. Doochul Shin and Sandeep K. Gupta. A new circuit simplification method for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 1566–1571, 2011.
[SGC11]
Zurück zum Zitat Saeed Shamshiri, Amirali Ghofrani, and Kwang-Ting Cheng. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference, pages 1–10, 2011. Saeed Shamshiri, Amirali Ghofrani, and Kwang-Ting Cheng. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference, pages 1–10, 2011.
[SGT+08]
Zurück zum Zitat Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions Semiconductor Manufacturing, 21(1): 3–13, 2008.CrossRef Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions Semiconductor Manufacturing, 21(1): 3–13, 2008.CrossRef
[SGTT08]
Zurück zum Zitat Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas. EVAL: Utilizing processors with variation-induced timing errors. In International Symposium on Microarchitecture, pages 423–434, 2008. Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas. EVAL: Utilizing processors with variation-induced timing errors. In International Symposium on Microarchitecture, pages 423–434, 2008.
[SKF+09]
Zurück zum Zitat André Sülflow, Ulrich Kuhne, Goerschwin Fey, Daniel Grosse, and Rolf Drechsler. WoLFram – a word level framework for formal verification. In IEEE/IFIP International Symposium on Rapid System Prototyping, pages 11–17, 2009. André Sülflow, Ulrich Kuhne, Goerschwin Fey, Daniel Grosse, and Rolf Drechsler. WoLFram – a word level framework for formal verification. In IEEE/IFIP International Symposium on Rapid System Prototyping, pages 11–17, 2009.
[SRL+11]
Zurück zum Zitat Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, and Davide Bertozzi. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of Design, Automation and Test in Europe, pages 661–666, 2011. Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, and Davide Bertozzi. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of Design, Automation and Test in Europe, pages 661–666, 2011.
[SV07]
Zurück zum Zitat Sean Safarpour and Andreas Veneris. Abstraction and refinement techniques in automated design debugging. In Proceedings of Design, Automation and Test in Europe, pages 1182–1187, 2007. Sean Safarpour and Andreas Veneris. Abstraction and refinement techniques in automated design debugging. In Proceedings of Design, Automation and Test in Europe, pages 1182–1187, 2007.
[SVAV05]
Zurück zum Zitat Alexander Smith, Andreas Veneris, Moayad Fahim Ali, and Anastasios Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(10):1606–1621, 2005. Alexander Smith, Andreas Veneris, Moayad Fahim Ali, and Anastasios Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(10):1606–1621, 2005.
[SVD08]
Zurück zum Zitat Sean Safarpour, Andreas G Veneris, and Rolf Drechsler. Improved SAT-based reachability analysis with observability don’t cares. Journal of Satisfiability, Boolean Modeling and Computation, 5:1–25, 2008. Sean Safarpour, Andreas G Veneris, and Rolf Drechsler. Improved SAT-based reachability analysis with observability don’t cares. Journal of Satisfiability, Boolean Modeling and Computation, 5:1–25, 2008.
[TBG11]
Zurück zum Zitat Desta Tadesse, R. Iris Bahar, and Joel Grodstein. Test vector generation for post-silicon delay testing using SAT-based decision problems. Journal of Electronic Testing: Theory and Applications, 27(2):123–136, 2011. Desta Tadesse, R. Iris Bahar, and Joel Grodstein. Test vector generation for post-silicon delay testing using SAT-based decision problems. Journal of Electronic Testing: Theory and Applications, 27(2):123–136, 2011.
[TBW+09]
Zurück zum Zitat James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, and Tanay Karnik. Resilient circuits - enabling energy-efficient performance and reliability. In Proceedings of the International Conference on Computer-Aided Design, pages 71–73, 2009. James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, and Tanay Karnik. Resilient circuits - enabling energy-efficient performance and reliability. In Proceedings of the International Conference on Computer-Aided Design, pages 71–73, 2009.
[TGR+12]
Zurück zum Zitat Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, and Ulf Schlichtmann. Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs. In International Conference on Hardware/Software Codesign and System Synthesis, pages 181–186, 2012. Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, and Ulf Schlichtmann. Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs. In International Conference on Hardware/Software Codesign and System Synthesis, pages 181–186, 2012.
[THPM+10]
Zurück zum Zitat Yanjing Li Ted Hong, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, and Subhasish Mitra. QED: Quick error detection tests for effective post-silicon validation. In Proceedings of the International Test Conference, pages 1–10, 2010. Yanjing Li Ted Hong, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, and Subhasish Mitra. QED: Quick error detection tests for effective post-silicon validation. In Proceedings of the International Test Conference, pages 1–10, 2010.
[Tse68]
Zurück zum Zitat Grigori S Tseitin. On the complexity of derivation in the propositional calculus. Zapiski nauchnykh seminarov LOMI, 8:234–259, 1968. Grigori S Tseitin. On the complexity of derivation in the propositional calculus. Zapiski nauchnykh seminarov LOMI, 8:234–259, 1968.
[TX07]
Zurück zum Zitat Shan Tang and Qiang Xu. A multi-core debug platform for NoC-based systems. In Proceedings of Design, Automation and Test in Europe, pages 870–875, 2007. Shan Tang and Qiang Xu. A multi-core debug platform for NoC-based systems. In Proceedings of Design, Automation and Test in Europe, pages 870–875, 2007.
[VARR11]
Zurück zum Zitat Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan. MACACO: Modeling and analysis of circuits for approximate computing. In Proceedings of the International Conference on Computer-Aided Design, pages 667–673, 2011. Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan. MACACO: Modeling and analysis of circuits for approximate computing. In Proceedings of the International Conference on Computer-Aided Design, pages 667–673, 2011.
[Vel05]
Zurück zum Zitat Miroslav N Velev. Comparison of schemes for encoding unobservability in translation to SAT. In Proceedings of the ASP Design Automation Conference, pages 1056–1059, 2005. Miroslav N Velev. Comparison of schemes for encoding unobservability in translation to SAT. In Proceedings of the ASP Design Automation Conference, pages 1056–1059, 2005.
[Ver02]
Zurück zum Zitat SystemC Version. 2.0 user’s guide. Open SystemC Initiative, 2002. SystemC Version. 2.0 user’s guide. Open SystemC Initiative, 2002.
[VG09]
Zurück zum Zitat Bart Vermeulen and Kees Goossens. A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs. In International Symposium on VLSI Design, Automation and Test, pages 183–186, 2009. Bart Vermeulen and Kees Goossens. A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs. In International Symposium on VLSI Design, Automation and Test, pages 183–186, 2009.
[VH99]
Zurück zum Zitat Andreas Veneris and Ibrahim N Hajj. Design error diagnosis and correction via test vector simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1803–1816, 1999. Andreas Veneris and Ibrahim N Hajj. Design error diagnosis and correction via test vector simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1803–1816, 1999.
[VWB02]
Zurück zum Zitat Baart Vermeulen, Tom Waayers, and Sjaak Bakker. IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips. In Proceedings of the International Test Conference, pages 55–63, 2002. Baart Vermeulen, Tom Waayers, and Sjaak Bakker. IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips. In Proceedings of the International Test Conference, pages 55–63, 2002.
[VWG02]
Zurück zum Zitat Bart Vermeulen, Tom Waayers, and Sandeep Kumar Goel. Core-based scan architecture for silicon debug. In Proceedings of the International Test Conference, pages 638–647, 2002. Bart Vermeulen, Tom Waayers, and Sandeep Kumar Goel. Core-based scan architecture for silicon debug. In Proceedings of the International Test Conference, pages 638–647, 2002.
[WC09]
Zurück zum Zitat Lu Wan and Deming Chen. Dynatune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proceedings of the International Conference on Computer-Aided Design, pages 172–179, 2009. Lu Wan and Deming Chen. Dynatune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proceedings of the International Conference on Computer-Aided Design, pages 172–179, 2009.
[WCCC12]
Zurück zum Zitat Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, and Tien-Fu Chen. NUDA: A non-uniform debugging architecture and nonintrusive race detection for many-core systems. IEEE Transactions Computers, 61(2):199–212, 2012.MathSciNetCrossRef Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, and Tien-Fu Chen. NUDA: A non-uniform debugging architecture and nonintrusive race detection for many-core systems. IEEE Transactions Computers, 61(2):199–212, 2012.MathSciNetCrossRef
[WLRI87]
Zurück zum Zitat John A Waicukauski, Eric Lindbloom, Barry K Rosen, and Vijay S Iyengar. Transition fault simulation. IEEE Design & Test of Computers, 4(2):32–38, 1987. John A Waicukauski, Eric Lindbloom, Barry K Rosen, and Vijay S Iyengar. Transition fault simulation. IEEE Design & Test of Computers, 4(2):32–38, 1987.
[XD10]
Zurück zum Zitat Lin Xie and Azadeh Davoodi. Representative path selection for post-silicon timing prediction under variability. In Proceedings of the Design Automation Conference, pages 386–391, 2010. Lin Xie and Azadeh Davoodi. Representative path selection for post-silicon timing prediction under variability. In Proceedings of the Design Automation Conference, pages 386–391, 2010.
[XD11]
Zurück zum Zitat Lin Xie and Azadeh Davoodi. Bound-based statistically-critical path extraction under process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(1):59–71, 2011.CrossRef Lin Xie and Azadeh Davoodi. Bound-based statistically-critical path extraction under process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(1):59–71, 2011.CrossRef
[XDS10]
Zurück zum Zitat Lin Xie, Azadeh Davoodi, and Kewal K. Saluja. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. In Proceedings of the Design Automation Conference, pages 274–279, 2010. Lin Xie, Azadeh Davoodi, and Kewal K. Saluja. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. In Proceedings of the Design Automation Conference, pages 274–279, 2010.
[YNV09]
Zurück zum Zitat Yu-Shen Yang, Nicola Nicolici, and Andreas G. Veneris. Automated data analysis solutions to silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 982–987, 2009. Yu-Shen Yang, Nicola Nicolici, and Andreas G. Veneris. Automated data analysis solutions to silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 982–987, 2009.
[YPK10]
Zurück zum Zitat Hyunbean Yi, Sungju Park, and Sandip Kundu. On-chip support for NoC-based SoC debugging. IEEE Transactions on Circuits and Systems, 57-I(7):1608–1617, 2010.MathSciNet Hyunbean Yi, Sungju Park, and Sandip Kundu. On-chip support for NoC-based SoC debugging. IEEE Transactions on Circuits and Systems, 57-I(7):1608–1617, 2010.MathSciNet
[YT08]
Zurück zum Zitat Joon-Sung Yang and Nur A. Touba. Expanding trace buffer observation window for in-system silicon debug through selective capture. In Proceedings of the VLSI Test Symposium, pages 345–351, 2008. Joon-Sung Yang and Nur A. Touba. Expanding trace buffer observation window for in-system silicon debug through selective capture. In Proceedings of the VLSI Test Symposium, pages 345–351, 2008.
[YT13]
Zurück zum Zitat Joon-Sung Yang and Nur A Touba. Improved trace buffer observation via selective data capture using 2-d compaction for post-silicon debug. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 21(2):320–328, 2013. Joon-Sung Yang and Nur A Touba. Improved trace buffer observation via selective data capture using 2-d compaction for post-silicon debug. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 21(2):320–328, 2013.
[ZCY+07]
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[ZGC+10]
Zurück zum Zitat Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, and Ken Amstutz. Scan based speed-path debug for a microprocessor. In European Test Symposium, pages 207–212, 2010. Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, and Ken Amstutz. Scan based speed-path debug for a microprocessor. In European Test Symposium, pages 207–212, 2010.
Metadaten
Titel
Analyzing Timing Variations
verfasst von
Mehdi Dehbashi
Görschwin Fey
Copyright-Jahr
2015
DOI
https://doi.org/10.1007/978-3-319-09309-3_6

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